luke
/
klayout
mirror of https://github.com/KLayout/klayout.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Write short versions of LVS and L2N DB by default.

This commit is contained in:
Matthias Koefferlein 2019-07-12 17:43:43 +02:00
parent 85717beca6
commit a47190f3ab
17 changed files with 1550 additions and 1717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/drc/drc/built-in-macros/_drc_engine.rb
View File

@ -761,7 +761,7 @@ module DRC
# %DRC%
# @name report_netlist
# @brief Specifies an extracted netlist report for output
# @synopsis report_netlist([ filename ])
# @synopsis report_netlist([ filename [, long ] ])
# This method applies to runsets creating a netlist through
# extraction. Extraction happens when connections and/or device
# extractions are made. If this statement is used, the extracted
@ -769,13 +769,16 @@ module DRC
# layout-to-netlist report (L2N database) and shown in the
# netlist browser window. If a file name is given, the report
# will also be written to the given file.
# If a file name is given and "long" is true, a verbose
# version of the L2N DB format will be used.
def report_netlist(filename = nil)
def report_netlist(filename = nil, long = nil)
@show_l2ndb = true
if filename
filename.is_a?(String) || raise("Argument must be string in report_netlist")
end
@output_l2ndb_file = filename
@output_l2ndb_long = long
end
# %DRC%
@ -1415,7 +1418,7 @@ CODE
l2ndb_file = _make_path(@output_l2ndb_file)
info("Writing netlist database: #{l2ndb_file} ..")
@netter.l2n_data.write_l2n(l2ndb_file)
@netter.l2n_data.write_l2n(l2ndb_file, !@output_l2ndb_long)
end

10
src/lvs/lvs/built-in-macros/_lvs_engine.rb
View File

@ -47,7 +47,7 @@ module LVS
lvsdb_file = _make_path(@output_lvsdb_file)
info("Writing LVS database: #{lvsdb_file} ..")
@netter.lvs_data.write(lvsdb_file)
@netter.lvs_data.write(lvsdb_file, !@output_lvsdb_long)
end
@ -56,11 +56,12 @@ module LVS
# %LVS%
# @name report_lvs
# @brief Specifies an LVS report for output
# @synopsis report_lvs([ filename ])
# @synopsis report_lvs([ filename [, long ] ])
# After the comparison step, the LVS database will be shown
# in the netlist database browser in a cross-reference view.
# If a filename is given, the LVS database is also written to
# this file.
# this file. If a file name is given and "long" is true, a
# verbose version of the LVS DB format will be used.
#
# If this method is called together with report_netlist and two files each, two
# files can be generated - one for the extracted netlist (L2N database) and one for the
@ -70,12 +71,13 @@ module LVS
#
# report_lvs is only effective if a comparison step is included.
def report_lvs(filename = nil)
def report_lvs(filename = nil, long = nil)
@show_l2ndb = true
if filename
filename.is_a?(String) || raise("Argument must be string in report_lvs")
end
@output_lvsdb_file = filename
@output_lvsdb_long = long
end
# %LVS%

2
src/lvs/unit_tests/lvsBasicTests.cc
View File

@ -47,7 +47,7 @@ TEST(1)
"# Reports generated\n"
"\n"
"# LVS report to inv.lvsdb\n"
"report_lvs('%s')\n"
"report_lvs('%s', true)\n"
"\n"
"# Write extracted netlist to inv_extracted.cir\n"
"target_netlist('%s', write_spice, 'Extracted by KLayout')\n"

2
testdata/lvs/inv.lvs vendored
View File

@ -6,7 +6,7 @@ deep
# Reports generated
# LVS report to inv.lvsdb
report_lvs("inv.lvsdb")
report_lvs("inv.lvsdb", true)
# Write extracted netlist to inv_extracted.cir
target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")

2
testdata/lvs/inv2.lvs vendored
View File

@ -6,7 +6,7 @@ deep
# Reports generated
# LVS report to inv.lvsdb
report_lvs("inv.lvsdb")
report_lvs("inv.lvsdb", true)
# Write extracted netlist to inv_extracted.cir
target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")

410
testdata/lvs/inv2.lvsdb vendored
View File

@ -1,247 +1,201 @@
#%lvsdb-klayout
# Layout
layout(
top(INVERTER_WITH_DIODES)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 'NWELL (1/0)')
layer(l4 'POLY (5/0)')
layer(l8 'CONTACT (6/0)')
layer(l11 'METAL1 (7/0)')
layer(l12 'METAL1_LABEL (7/1)')
layer(l13 'VIA1 (8/0)')
layer(l14 'METAL2 (9/0)')
layer(l15 'METAL2_LABEL (9/1)')
layer(l7)
layer(l1)
layer(l9)
layer(l5)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l1 l9 l5 l10)
connect(l11 l8 l11 l12 l13)
connect(l12 l11 l12)
connect(l13 l11 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l7 l7)
connect(l1 l8 l1)
connect(l9 l3 l8 l9)
connect(l5 l8 l5)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l1 (-575 -750) (450 1500))
J(
W(INVERTER_WITH_DIODES)
U(0.001)
L(l3 'NWELL (1/0)')
L(l4 'POLY (5/0)')
L(l8 'CONTACT (6/0)')
L(l11 'METAL1 (7/0)')
L(l12 'METAL1_LABEL (7/1)')
L(l13 'VIA1 (8/0)')
L(l14 'METAL2 (9/0)')
L(l15 'METAL2_LABEL (9/1)')
L(l7)
L(l1)
L(l9)
L(l5)
L(l10)
C(l3 l3 l9)
C(l4 l4 l8)
C(l8 l4 l8 l11 l1 l9 l5 l10)
C(l11 l8 l11 l12 l13)
C(l12 l11 l12)
C(l13 l11 l13 l14)
C(l14 l13 l14 l15)
C(l15 l14 l15)
C(l7 l7)
C(l1 l8 l1)
C(l9 l3 l8 l9)
C(l5 l8 l5)
C(l10 l8 l10)
G(l7 SUBSTRATE)
G(l10 SUBSTRATE)
D(D$PMOS PMOS
T(S
R(l1 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
T(G
R(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (450 1500))
T(D
R(l1 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
T(B
R(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l5 (-575 -450) (450 900))
D(D$NMOS NMOS
T(S
R(l5 (-575 -450) (450 900))
)
terminal(G
rect(l4 (-125 -450) (250 900))
T(G
R(l4 (-125 -450) (250 900))
)
terminal(D
rect(l5 (125 -450) (450 900))
T(D
R(l5 (125 -450) (450 900))
)
terminal(B
rect(l7 (-125 -450) (250 900))
T(B
R(l7 (-125 -450) (250 900))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INVERTER_WITH_DIODES
# Circuit boundary
rect((0 0) (3000 6150))
# Nets with their geometries
net(1 name(IN)
rect(l4 (900 50) (250 1050))
rect(l4 (-250 0) (250 3100))
rect(l4 (-250 0) (250 1650))
rect(l4 (-800 -3100) (550 400))
rect(l8 (-450 -300) (200 200))
rect(l11 (-300 -300) (400 400))
rect(l12 (-201 -201) (2 2))
X(INVERTER_WITH_DIODES
R((0 0) (3000 6150))
N(1 I(IN)
R(l4 (900 50) (250 1050))
R(l4 (-250 0) (250 3100))
R(l4 (-250 0) (250 1650))
R(l4 (-800 -3100) (550 400))
R(l8 (-450 -300) (200 200))
R(l11 (-300 -300) (400 400))
R(l12 (-201 -201) (2 2))
)
net(2 name(VDD)
rect(l3 (0 2950) (3000 3200))
rect(l8 (-2450 -1800) (200 200))
rect(l8 (-200 300) (200 200))
rect(l8 (-200 300) (200 200))
rect(l8 (1400 -800) (200 200))
rect(l8 (-200 300) (200 200))
rect(l11 (-1850 -1200) (300 1600))
rect(l11 (1300 -1200) (300 1200))
rect(l13 (-1850 -800) (200 200))
rect(l13 (-200 300) (200 200))
rect(l13 (1400 -700) (200 200))
rect(l13 (-200 300) (200 200))
rect(l14 (-2350 -850) (3000 1000))
rect(l15 (-151 -851) (2 2))
rect(l1 (-2401 -851) (450 1500))
rect(l9 (1050 -1200) (600 1200))
N(2 I(VDD)
R(l3 (0 2950) (3000 3200))
R(l8 (-2450 -1800) (200 200))
R(l8 (-200 300) (200 200))
R(l8 (-200 300) (200 200))
R(l8 (1400 -800) (200 200))
R(l8 (-200 300) (200 200))
R(l11 (-1850 -1200) (300 1600))
R(l11 (1300 -1200) (300 1200))
R(l13 (-1850 -800) (200 200))
R(l13 (-200 300) (200 200))
R(l13 (1400 -700) (200 200))
R(l13 (-200 300) (200 200))
R(l14 (-2350 -850) (3000 1000))
R(l15 (-151 -851) (2 2))
R(l1 (-2401 -851) (450 1500))
R(l9 (1050 -1200) (600 1200))
)
net(3 name(OUT)
rect(l8 (1300 4350) (200 200))
rect(l8 (-200 300) (200 200))
rect(l8 (-200 300) (200 200))
rect(l8 (-200 -5250) (200 200))
rect(l8 (-200 300) (200 200))
rect(l11 (-250 3250) (300 1400))
rect(l11 (-300 -4600) (300 3200))
rect(l11 (-300 -2900) (450 400))
rect(l11 (-450 -1550) (300 850))
rect(l12 (-51 499) (2 2))
rect(l1 (-351 2649) (450 1500))
rect(l5 (-450 -5500) (450 900))
N(3 I(OUT)
R(l8 (1300 4350) (200 200))
R(l8 (-200 300) (200 200))
R(l8 (-200 300) (200 200))
R(l8 (-200 -5250) (200 200))
R(l8 (-200 300) (200 200))
R(l11 (-250 3250) (300 1400))
R(l11 (-300 -4600) (300 3200))
R(l11 (-300 -2900) (450 400))
R(l11 (-450 -1550) (300 850))
R(l12 (-51 499) (2 2))
R(l1 (-351 2649) (450 1500))
R(l5 (-450 -5500) (450 900))
)
net(4 name(VSS)
rect(l8 (550 300) (200 200))
rect(l8 (-200 300) (200 200))
rect(l8 (1400 -550) (200 200))
rect(l8 (-200 300) (200 200))
rect(l11 (-1850 -1100) (300 1050))
rect(l11 (1300 -1050) (300 1200))
rect(l13 (-1850 -1100) (200 200))
rect(l13 (-200 300) (200 200))
rect(l13 (1400 -700) (200 200))
rect(l13 (-200 300) (200 200))
rect(l14 (-2350 -850) (3000 1000))
rect(l15 (-151 -851) (2 2))
rect(l5 (-2401 49) (450 900))
rect(l10 (1050 -900) (600 1200))
N(4 I(VSS)
R(l8 (550 300) (200 200))
R(l8 (-200 300) (200 200))
R(l8 (1400 -550) (200 200))
R(l8 (-200 300) (200 200))
R(l11 (-1850 -1100) (300 1050))
R(l11 (1300 -1050) (300 1200))
R(l13 (-1850 -1100) (200 200))
R(l13 (-200 300) (200 200))
R(l13 (1400 -700) (200 200))
R(l13 (-200 300) (200 200))
R(l14 (-2350 -850) (3000 1000))
R(l15 (-151 -851) (2 2))
R(l5 (-2401 49) (450 900))
R(l10 (1050 -900) (600 1200))
)
# Devices and their connections
device(1 D$PMOS
location(1025 4950)
param(L 0.25)
param(W 1.5)
param(AS 0.675)
param(AD 0.675)
param(PS 3.9)
param(PD 3.9)
terminal(S 2)
terminal(G 1)
terminal(D 3)
terminal(B 2)
D(1 D$PMOS
Y(1025 4950)
E(L 0.25)
E(W 1.5)
E(AS 0.675)
E(AD 0.675)
E(PS 3.9)
E(PD 3.9)
T(S 2)
T(G 1)
T(D 3)
T(B 2)
)
device(2 D$NMOS
location(1025 650)
param(L 0.25)
param(W 0.9)
param(AS 0.405)
param(AD 0.405)
param(PS 2.7)
param(PD 2.7)
terminal(S 4)
terminal(G 1)
terminal(D 3)
terminal(B 4)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INVERTER_WITH_DIODES
# Nets
net(1 name(VSS))
net(2 name(IN))
net(3 name(OUT))
net(4 name(VDD))
# Outgoing pins and their connections to nets
pin(1)
pin(2)
pin(3)
pin(4)
# Devices and their connections
device(1 PMOS
name(P)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(G 2)
terminal(D 3)
terminal(B 4)
)
device(2 NMOS
name(N)
param(L 0.25)
param(W 0.9)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 2)
terminal(D 1)
terminal(B 1)
)
)
)
# Cross reference
xref(
circuit(INVERTER_WITH_DIODES INVERTER_WITH_DIODES match
xref(
net(1 2 match)
net(3 3 match)
net(2 4 match)
net(4 1 match)
pin(() 0 match)
pin(() 1 match)
pin(() 2 match)
pin(() 3 match)
device(2 2 match)
device(1 1 match)
D(2 D$NMOS
Y(1025 650)
E(L 0.25)
E(W 0.9)
E(AS 0.405)
E(AD 0.405)
E(PS 2.7)
E(PD 2.7)
T(S 4)
T(G 1)
T(D 3)
T(B 4)
)
)
)
H(
X(INVERTER_WITH_DIODES
N(1 I(VSS))
N(2 I(IN))
N(3 I(OUT))
N(4 I(VDD))
P(1)
P(2)
P(3)
P(4)
D(1 PMOS
I(P)
E(L 0.25)
E(W 1.5)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 4)
T(G 2)
T(D 3)
T(B 4)
)
D(2 NMOS
I(N)
E(L 0.25)
E(W 0.9)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(G 2)
T(D 1)
T(B 1)
)
)
)
Z(
X(INVERTER_WITH_DIODES INVERTER_WITH_DIODES 1
Z(
N(1 2 1)
N(3 3 1)
N(2 4 1)
N(4 1 1)
P(() 0 1)
P(() 1 1)
P(() 2 1)
P(() 3 1)
D(2 2 1)
D(1 1 1)
)
)
)

2
testdata/lvs/ringo_simple.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

2
testdata/lvs/ringo_simple_blackboxing.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

2
testdata/lvs/ringo_simple_implicit_connections.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

1766
testdata/lvs/ringo_simple_io.lvsdb vendored
View File

File diff suppressed because it is too large Load Diff

1048
testdata/lvs/ringo_simple_io2.l2n vendored
View File

File diff suppressed because it is too large Load Diff

2
testdata/lvs/ringo_simple_io2.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
report_netlist($lvs_test_target_l2n)
# Write extracted netlist to extracted.cir using a special

2
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "top")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

2
testdata/lvs/ringo_simple_pin_swapping.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

2
testdata/lvs/ringo_simple_same_device_classes.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")

2
testdata/lvs/ringo_simple_simplification.lvs vendored
View File

@ -1,7 +1,7 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb)
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")

2
testdata/lvs/vexriscv.lvs vendored
View File

@ -2,7 +2,7 @@
source($lvs_test_source)
# will get pretty big:
# report_lvs($lvs_test_target_lvsdb)
# report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout")