mirror of https://github.com/KLayout/klayout.git
WIP: more LVS doc.
This commit is contained in:
Matthias Koefferlein
parent
437ead7699
commit
20c8c6bdaa
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@ -14,6 +14,9 @@
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<topic href="/manual/lvs_overview.xml"/>
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<topic href="/manual/lvs_intro.xml"/>
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<topic href="/manual/lvs_devices.xml"/>
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<topic href="/manual/lvs_device_classes.xml"/>
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<topic href="/manual/lvs_device_extractors.xml"/>
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<topic href="/manual/lvs_io.xml"/>
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<!--
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<topic href="/manual/lvs_hierarchy.xml"/>
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@ -21,7 +24,7 @@
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<topic href="/manual/lvs_reference.xml"/>
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<topic href="/manual/lvs_compare.xml"/>
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<topic href="/manual/lvs_tweaks.xml"/>
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<topuresic href="/manual/lvs_browser.xml"/>
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<topic href="/manual/lvs_browser.xml"/>
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-->
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</topics>
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@ -0,0 +1,17 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "klayout_doc.dtd">
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<doc>
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<title>LVS Device Classes</title>
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<keyword name="LVS"/>
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<keyword name="LVS Device Classes"/>
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<h2-index/>
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<p>
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LVS (and also DRC as far as netlist extraction is concerned) provides
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</p>
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</doc>
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@ -0,0 +1,250 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "klayout_doc.dtd">
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<doc>
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<title>LVS Device Classes</title>
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<keyword name="LVS"/>
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<keyword name="LVS Device Classes"/>
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<h2-index/>
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<p>
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KLayout implements a variety of standard device classes. These device classes
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are the basis for forming particular incarnations of device classes.
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For example, the MOS4 class is the basis for the specific device classes
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for NMOS and PMOS transistors.
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</p>
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<h2>Resistor</h2>
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<p>
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<img src="/manual/res_schematic.png"/>
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</p>
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<p>
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The plain resistor has two terminals, A and B. It features the following
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parameters:
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</p>
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<ul>
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<li><b><tt>R</tt></b>: The resistance value in Ohm</li>
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<li><b><tt>L</tt></b>: The length in µm</li>
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<li><b><tt>W</tt></b>: The width in µm</li>
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<li><b><tt>A</tt></b>: The area of the resistor area in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the resistor area in µm</li>
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</ul>
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<p>
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Resistors can combine in parallel or serial fashion.
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</p>
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<p>
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In SPICE, plain resistors are represented by the "R" element.
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The API class is <class_doc href="DeviceClassResistor"/>.
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</p>
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<h2>Resistor with bulk terminal</h2>
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<p>
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<img src="/manual/res_with_bulk_schematic.png"/>
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</p>
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<p>
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The resistor with bulk terminal is an extension of the plain resistor.
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If has the same parameters, but one additional terminal (W) which connects to
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the area the resistor sits in (e.g. well or substrate).
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</p>
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<p>
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Resistors with bulk can combine in parallel or serial fashion if their
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bulk terminals are connected to the same net.
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</p>
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<p>
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The API class of the resistor with bulk is <class_doc href="DeviceClassResistorWithBulk"/>.
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</p>
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<h2>Capacitor</h2>
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<p>
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<img src="/manual/cap_schematic.png"/>
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</p>
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<p>
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The plain capacitor has two terminals, A and B. It features the following
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parameters:
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</p>
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<ul>
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<li><b><tt>C</tt></b>: The capacitance value in Farad</li>
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<li><b><tt>A</tt></b>: The area of the capacitor area in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the capacitor area in µm</li>
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</ul>
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<p>
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In SPICE, plain capacitors are represented by the "C" element.
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The API class is <class_doc href="DeviceClassCapacitor"/>.
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</p>
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<h2>Capacitor with bulk terminal</h2>
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<p>
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<img src="/manual/cap_with_bulk_schematic.png"/>
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</p>
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<p>
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The capacitor with bulk terminal is an extension of the plain capacitor.
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If has the same parameters, but one additional terminal (W) which connects to
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the area the capacitor sits in (e.g. well or substrate).
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</p>
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<p>
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Capacitors with bulk can combine in parallel or serial fashion if their
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bulk terminals are connected to the same net.
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</p>
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<p>
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The API class of the capacitor with bulk is <class_doc href="DeviceClassCapacitorWithBulk"/>.
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</p>
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<h2>Diode</h2>
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<p>
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<img src="/manual/diode_schematic.png"/>
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</p>
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<p>
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Diodes have two terminals, A and C for anode and cathode. Diodes
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feature the following parameters:
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</p>
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<ul>
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<li><b><tt>A</tt></b>: The area of the diode in µm²</li>
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<li><b><tt>P</tt></b>: The perimeter of the diode in µm</li>
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</ul>
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<p>
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Diodes combine in parallel (A to A and C to C). In this case
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their areas and perimeters will add.
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</p>
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<p>
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In SPICE, diodes are represented by the "D" element using the
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device class name as the model name.
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The API class is <class_doc href="DeviceClassDiode"/>.
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</p>
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<h2>MOS transistor</h2>
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<p>
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<img src="/manual/mos3_schematic.png"/>
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</p>
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<p>
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Three-terminal MOS transistors have terminals S, G and D for source, gate and drain.
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S and D are commutable. They feature the following parameters:
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</p>
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<ul>
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<li><b><tt>W</tt></b>: The gate width in µm</li>
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<li><b><tt>L</tt></b>: The gate (channel) length in µm</li>
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<li><b><tt>AS</tt></b>: The source area in µm²</li>
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<li><b><tt>PS</tt></b>: The source perimeter in µm</li>
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<li><b><tt>AD</tt></b>: The drain area in µm²</li>
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<li><b><tt>PD</tt></b>: The drain perimeter in µm</li>
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</ul>
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<p>
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MOS3 transistors combine in parallel when the source/drains and gates are connected
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and their gate lengths are identical.
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In this case their widths, areas and perimeters will add.
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</p>
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<h2>MOS transistor with bulk</h2>
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<p>
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The API class of the three-terminal MOS transistor is <class_doc href="DeviceClassMOS3"/>.
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</p>
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<p>
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<img src="/manual/mos4_schematic.png"/>
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</p>
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<p>
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The four-terminal transistor is an extension of the three-terminal one and
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offers an additional bulk terminal (B). It is probably the most prominent
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transistor device as the four-terminal version is compatible with the SPICE
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"M" element.
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</p>
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<p>
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MOS transistors with bulk can combine in parallel the same way the three-terminal
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versions do if their bulk terminals are connected to the same net.
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</p>
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<p>
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In SPICE, MOS4 devices are represented by the "M" element with the
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device class name as the model name.
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The API class is <class_doc href="DeviceClassDiode"/>.
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</p>
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<h2>Bipolar transistor</h2>
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<p>
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<img src="/manual/bjt3_schematic.png"/>
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</p>
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<p>
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The three-terminal bipolar transistor can be either NPN or PNP type.
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In KLayout, this device type can represent both lateral and vertical
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types.
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The parameters are:
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</p>
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<ul>
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<li><b><tt>AE</tt></b>: The emitter area in µm²</li>
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<li><b><tt>PE</tt></b>: The emitter perimeter in µm</li>
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<li><b><tt>NE</tt></b>: The emitter count (initially 1)</li>
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<li><b><tt>AB</tt></b>: The base area in µm²</li>
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<li><b><tt>PB</tt></b>: The base perimeter in µm</li>
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<li><b><tt>AC</tt></b>: The collector area in µm²</li>
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<li><b><tt>PC</tt></b>: The collector perimeter in µm</li>
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</ul>
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<p>
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Upon extraction, multi-emitter versions are extracted as multiple devices - one
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for each emitter area - and NE = 1. Bipolar transistors combine when in parallel.
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In this case, their emitter parameters AE, PE and NE are added.
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</p>
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<p>
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In SPICE, BJT3 devices are represented by the "Q" element with the
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device class name as the model name.
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The API class is <class_doc href="DeviceClassBJT3"/>.
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</p>
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<h2>Bipolar transistor with substrate</h2>
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<p>
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<img src="/manual/bjt4_schematic.png"/>
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</p>
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<p>
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The four-terminal transistor is an extension of the three-terminal one and
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offers an additional bulk terminal (S).
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</p>
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<p>
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Bipolar transistors with bulk can combine in parallel the same way the three-terminal
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versions do if their bulk terminals are connected to the same net.
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</p>
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<p>
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In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the
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device class name as the model name.
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The API class is <class_doc href="DeviceClassBJT4"/>.
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</p>
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</doc>
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@ -0,0 +1,326 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE language SYSTEM "klayout_doc.dtd">
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<doc>
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<title>LVS Devices</title>
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<keyword name="LVS"/>
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<keyword name="LVS Devices"/>
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<h2-index/>
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<p>
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Device extractors and the actual "workers" of the device extraction process.
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KLayout comes with a variety of pre-built device extractors. It's possible to
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implement custom device extractors in the framework of LVS scripts (speaking
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Ruby).
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</p>
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<h2>Resistor extractors (<a href="/about/drc_ref_global.xml#resistor">resistor</a>
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and <a href="/about/drc_ref_global.xml#resistor_with_bulk">resistor_with_bulk</a>)</h2>
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<p>
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The resistor extractor assumes a layout which consists of a resistor "wire"
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and two caps (contacts). The wire is specified with the layer symbol "R",
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the caps are specified with the layer symbol "C":
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</p>
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<p>
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<img src="/manual/res_ex_layout.png"/>
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</p>
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<p>
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The extractor will compute the resistance from the number of squares
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and the sheet resistance. The sheet resistance needs to be given
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when creating the extractor:
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</p>
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<pre>sheet_rho = 0.5
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model_name = "RES"
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extract_devices(resistor(model_name, sheet_rho), { "R" => res_layer, "C" => cap_layer })</pre>
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<p>
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The plain resistor offers two terminals which it outputs on "tA" and "tB" terminal layers.
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If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "C" layer.
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respectively.
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</p>
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<p>
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<img src="/manual/res_ex_ta.png"/>
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</p>
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<p>
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<img src="/manual/res_ex_tb.png"/>
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</p>
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<p>
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For the resistor with bulk, the wire area is output on the "tW" terminal layer as
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the "W" terminal:
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</p>
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<p>
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<img src="/manual/res_ex_tw.png"/>
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</p>
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<h2>Capacitor extractors (<a href="/about/drc_ref_global.xml#capacitor">capacitor</a>
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and <a href="/about/drc_ref_global.xml#capacitor_with_bulk">capacitor_with_bulk</a>)</h2>
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<p>
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Capacitors are assumed to consist of two "plates" (vertical capacitors).
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The plates are on layers P1 and P2. The capacitor is extracted from the area where
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these two layers overlap.
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</p>
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<p>
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<img src="/manual/cap_ex_layout.png"/>
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</p>
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<p>
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The extractor will compute the capacitance from the area of the
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overlap and the capacitance per area (F/µm²) value.
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</p>
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<pre>area_cap = 1.5e-15
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model_name = "CAP"
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extract_devices(capacitor(model_name, area_cap), { "P1" => metal1, "P2" => metal2 })</pre>
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<p>
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The plain capacitor offers two terminals which it outputs on "tA" and "tB" terminal layers.
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If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "P1" and "P2" layers
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respectively.
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</p>
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<p>
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<img src="/manual/cap_ex_ta.png"/>
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</p>
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<p>
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<img src="/manual/cap_ex_tb.png"/>
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</p>
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<p>
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For the capacitor with bulk, the capacitor area is output on the "tW" terminal layer as
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the "W" terminal:
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</p>
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<p>
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<img src="/manual/cap_ex_tw.png"/>
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</p>
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<h2>Diode extractor (<a href="/about/drc_ref_global.xml#diode">diode</a>)</h2>
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<p>
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Diodes are assumed to consist of two vertical implant regions (wells, diffusion).
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One of the regions is p type ("P" layer) and the other "n" type ("N" layer).
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These layers also form the anode (p) and cathode (n) of the diode.
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</p>
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||||
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<p>
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<img src="/manual/diode_ex_layout.png"/>
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</p>
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||||
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<p>
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||||
The extractor will compute the capacitance from the area of the
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||||
overlap and the capacitance per area (F/µm²) value.
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</p>
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||||
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<pre>model_name = "DIODE"
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extract_devices(diode(model_name), { "P" => pplus, "N" => nwell })</pre>
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||||
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||||
<p>
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||||
The diode offers two terminals which it outputs on "tA" and "tC" terminal layers.
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||||
If "tA" is not specified, "A" terminals will be written on the "P" layer.
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If "tC" is not specified, "C" terminals will be written on the "N" layer.
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||||
</p>
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||||
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||||
<p>
|
||||
<img src="/manual/diode_ex_ta.png"/>
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||||
</p>
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||||
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||||
<p>
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||||
<img src="/manual/diode_ex_tc.png"/>
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||||
</p>
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||||
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||||
<h2>MOS transistor extractor (<a href="/about/drc_ref_global.xml#mos3">mos3</a> and <a href="/about/drc_ref_global.xml#mos4">mos4</a>)</h2>
|
||||
|
||||
<p>
|
||||
MOS transistors are recognized by their gate ("G" input) and source/drain ("SD" input) regions.
|
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Source and drain needs to be separated from the gate shape. The touching edges of gate and
|
||||
source/drain regions define the width of the device, the perpendicular dimension the gate length.
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||||
Because the separation of source/drain, the computation of gates and the separation of
|
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these for NMOS and PMOS devices, the "G" and "SD" layers are usually derived layers.
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As these usually won't participate in the connectivity, it's important to specify the
|
||||
"tS", "tD", "tG" and "tB" (for MOS4) layers explicitly and redirect the terminal shapes
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||||
to layers that really participate in connections.
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||||
</p>
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||||
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||||
<p>
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<img src="/manual/mos_ex_layout.png"/>
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</p>
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<pre>model_name = "PMOS"
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extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" => (active & poly), "W" => nwell,
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"tS" => active, "tD" => active, "tG" => poly, "tB" => nwell })</pre>
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||||
<p>
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The MOS3 device produces three terminals which it outputs on "tS", "tG" and "tD" terminal layers (source,
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gate and drain respectively):
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||||
</p>
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||||
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||||
<p>
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||||
<img src="/manual/mos_ex_ts.png"/>
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</p>
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||||
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||||
<p>
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||||
<img src="/manual/mos_ex_tg.png"/>
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||||
</p>
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||||
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||||
<p>
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||||
<img src="/manual/mos_ex_td.png"/>
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||||
</p>
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||||
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||||
<p>
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||||
The MOS4 device offers one more terminal (bulk) which it writes on "tB".
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||||
</p>
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||||
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||||
<p>
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||||
<img src="/manual/mos_ex_tb.png"/>
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||||
</p>
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||||
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||||
<h2>Bipolar transistor extractor (<a href="/about/drc_ref_global.xml#bjt3">bjt3</a> and <a href="/about/drc_ref_global.xml#bjt4">bjt4</a>)</h2>
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|
||||
<p>
|
||||
There are basically two kind of bipolar transistors: vertical and lateral ones.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Lateral transistors are formed by implant or diffusion wells creating a intermittent
|
||||
n/p structure on the wafer. The basic recognition region is the base region. The collector
|
||||
and emitter regions are inside or overlapping the base region and use the opposite doping
|
||||
than base: if the base region is n doped, then
|
||||
collector and emitter regions have to be p doped. The structure then forms a PNP transistor.
|
||||
KLayout recognizes lateral transistors when the base is <b>partially</b> covered by the collector region.
|
||||
For lateral transistors, the emitter is defined by the emitter region inside base. The
|
||||
collector region is defined by collector inside base and outside emitter.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_lateral.png"/> (lateral PNP transistor)
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors
|
||||
are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed
|
||||
by taking the collector as the substrate, nwell for the base and pplus implant for the emitter.
|
||||
KLayout recognizes a vertical bipolar transistor when the base is covered <b>entirely</b> by the
|
||||
collector or has <b>no collector at all</b> - this means the collector
|
||||
region can be empty (e.g. bulk).
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_vertical.png"/> (vertical PNP transistor)
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In both cases, there can be multiple emitter regions inside a base island. In this
|
||||
case, one transistor is extracted for each emitter region.
|
||||
</p>
|
||||
|
||||
<h3>Vertical bipolar transistors</h3>
|
||||
|
||||
<p>
|
||||
Vertical bipolar transistors take their inputs from "B" (base), "C" (collector)
|
||||
and "E" (emitter). "C" is optional:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Especially for bipolar devices it's important to device useful terminal output
|
||||
layers. Typically, the wells and diffusion areas will be connected through "contact",
|
||||
(not considering the Schottky diodes for now).
|
||||
So it's a good idea to send the terminals to the contact layer:
|
||||
</p>
|
||||
|
||||
<pre>model_name = "PNP"
|
||||
extract_devices(bjt3(model_name), { "C" => collector, "B" => base, "E" => emitter,
|
||||
"tC" => contact, "tB" => contact, "tE" => contact })</pre>
|
||||
|
||||
<p>
|
||||
The BJT3 device produces three terminals which it outputs on "tC", "tB" and "tE" terminal layers (collector,
|
||||
base and emitter respectively):
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_tc.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_te.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
If the collector region is empty (e.g. p substrate), the base shape is copied to the "tC" output layer
|
||||
for the collector terminal.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The BJT4 device offers one more terminal (substrate) which it writes on "tS". "tS" is
|
||||
a copy of the emitter shape but connected to the substrate terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_ts.png"/>
|
||||
</p>
|
||||
|
||||
<h3>Lateral bipolar transistors</h3>
|
||||
|
||||
<p>
|
||||
Lateral bipolar transistors also take their inputs from "B" (base), "C" (collector)
|
||||
and "E" (emitter). For lateral transistors, "C" is not optional and must not fully cover
|
||||
the base region. Apart from this, the use model for BJT3 and BJT4 extractors is
|
||||
identical for vertical and lateral transistors.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
A typical lateral transistor is formed by a collector ring and emitter
|
||||
island inside the base region:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The terminals produced by the bipolar transistor extractor in the lateral case are
|
||||
the same than for the vertical case, but with a different geometry:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_tc.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_te.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Again, for BJT4, "tS" is a copy of the emitter shape but connected to the substrate terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_ts.png"/>
|
||||
</p>
|
||||
|
||||
</doc>
|
||||
|
||||
|
|
@ -3,11 +3,9 @@
|
|||
|
||||
<doc>
|
||||
|
||||
<title>LVS Devices</title>
|
||||
<title>LVS Device Extractors</title>
|
||||
<keyword name="LVS"/>
|
||||
<keyword name="LVS Devices"/>
|
||||
|
||||
<h2-index/>
|
||||
<keyword name="LVS Device Extractors"/>
|
||||
|
||||
<h2>Device extractors and device classes</h2>
|
||||
|
||||
|
|
@ -15,555 +13,22 @@
|
|||
KLayout provides two concepts for handling device variety:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b>Device classes</b> are device categories. There are general categories such as
|
||||
resistors or MOS transistors. Specific categories can be created to represent specific
|
||||
incarnations - e.g. NMOS and PMOS devices. Device classes also determine how devices
|
||||
combine.</li>
|
||||
<li><b>Device extractors</b> are objects that analyze layout and produce devices. As for
|
||||
device classes, there are general device extractors. Each device extractor produces
|
||||
devices from a specific class.</li>
|
||||
</ul>
|
||||
|
||||
<h2>Device classes</h2>
|
||||
|
||||
<h3>Resistor</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The plain resistor has two terminals, A and B. It features the following
|
||||
parameters:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b><tt>R</tt></b>: The resistance value in Ohm</li>
|
||||
<li><b><tt>L</tt></b>: The length in µm</li>
|
||||
<li><b><tt>W</tt></b>: The width in µm</li>
|
||||
<li><b><tt>A</tt></b>: The area of the resistor area in µm²</li>
|
||||
<li><b><tt>P</tt></b>: The perimeter of the resistor area in µm</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
Resistors can combine in parallel or serial fashion.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In SPICE, plain resistors are represented by the "R" element.
|
||||
The API class is <class_doc href="DeviceClassResistor"/>.
|
||||
</p>
|
||||
|
||||
<h3>Resistor with bulk terminal</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_with_bulk_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The resistor with bulk terminal is an extension of the plain resistor.
|
||||
If has the same parameters, but one additional terminal (W) which connects to
|
||||
the area the resistor sits in (e.g. well or substrate).
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Resistors with bulk can combine in parallel or serial fashion if their
|
||||
bulk terminals are connected to the same net.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The API class of the resistor with bulk is <class_doc href="DeviceClassResistorWithBulk"/>.
|
||||
</p>
|
||||
|
||||
<h3>Capacitor</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The plain capacitor has two terminals, A and B. It features the following
|
||||
parameters:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b><tt>C</tt></b>: The capacitance value in Farad</li>
|
||||
<li><b><tt>A</tt></b>: The area of the capacitor area in µm²</li>
|
||||
<li><b><tt>P</tt></b>: The perimeter of the capacitor area in µm</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
In SPICE, plain capacitors are represented by the "C" element.
|
||||
The API class is <class_doc href="DeviceClassCapacitor"/>.
|
||||
</p>
|
||||
|
||||
<h3>Capacitor with bulk terminal</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_with_bulk_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The capacitor with bulk terminal is an extension of the plain capacitor.
|
||||
If has the same parameters, but one additional terminal (W) which connects to
|
||||
the area the capacitor sits in (e.g. well or substrate).
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Capacitors with bulk can combine in parallel or serial fashion if their
|
||||
bulk terminals are connected to the same net.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The API class of the capacitor with bulk is <class_doc href="DeviceClassCapacitorWithBulk"/>.
|
||||
</p>
|
||||
|
||||
<h3>Diode</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/diode_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Diodes have two terminals, A and C for anode and cathode. Diodes
|
||||
feature the following parameters:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b><tt>A</tt></b>: The area of the diode in µm²</li>
|
||||
<li><b><tt>P</tt></b>: The perimeter of the diode in µm</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
Diodes combine in parallel (A to A and C to C). In this case
|
||||
their areas and perimeters will add.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In SPICE, diodes are represented by the "D" element using the
|
||||
device class name as the model name.
|
||||
The API class is <class_doc href="DeviceClassDiode"/>.
|
||||
</p>
|
||||
|
||||
<h3>MOS transistor</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos3_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Three-terminal MOS transistors have terminals S, G and D for source, gate and drain.
|
||||
S and D are commutable. They feature the following parameters:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b><tt>W</tt></b>: The gate width in µm</li>
|
||||
<li><b><tt>L</tt></b>: The gate (channel) length in µm</li>
|
||||
<li><b><tt>AS</tt></b>: The source area in µm²</li>
|
||||
<li><b><tt>PS</tt></b>: The source perimeter in µm</li>
|
||||
<li><b><tt>AD</tt></b>: The drain area in µm²</li>
|
||||
<li><b><tt>PD</tt></b>: The drain perimeter in µm</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
MOS3 transistors combine in parallel when the source/drains and gates are connected
|
||||
and their gate lengths are identical.
|
||||
In this case their widths, areas and perimeters will add.
|
||||
</p>
|
||||
|
||||
<h3>MOS transistor with bulk</h3>
|
||||
|
||||
<p>
|
||||
The API class of the three-terminal MOS transistor is <class_doc href="DeviceClassMOS3"/>.
|
||||
<b>Device classes</b> are device categories. There are general categories such as
|
||||
resistors or MOS transistors. Specific categories can be created to represent specific
|
||||
incarnations - e.g. NMOS and PMOS devices. Device classes also determine how devices
|
||||
combine.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos4_schematic.png"/>
|
||||
</p>
|
||||
<p>Device classes are documented here: <link href="/manual/lvs_device_classes.xml"/>.</p>
|
||||
|
||||
<p>
|
||||
The four-terminal transistor is an extension of the three-terminal one and
|
||||
offers an additional bulk terminal (B). It is probably the most prominent
|
||||
transistor device as the four-terminal version is compatible with the SPICE
|
||||
"M" element.
|
||||
<b>Device extractors</b> are the actual worker objects that analyze layout and produce devices.
|
||||
As for device classes, there are general device extractors. Each device extractor produces
|
||||
devices from a specific class.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
MOS transistors with bulk can combine in parallel the same way the three-terminal
|
||||
versions do if their bulk terminals are connected to the same net.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In SPICE, MOS4 devices are represented by the "M" element with the
|
||||
device class name as the model name.
|
||||
The API class is <class_doc href="DeviceClassDiode"/>.
|
||||
</p>
|
||||
|
||||
<h3>Bipolar transistor</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt3_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The three-terminal bipolar transistor can be either NPN or PNP type.
|
||||
In KLayout, this device type can represent both lateral and vertical
|
||||
types.
|
||||
The parameters are:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b><tt>AE</tt></b>: The emitter area in µm²</li>
|
||||
<li><b><tt>PE</tt></b>: The emitter perimeter in µm</li>
|
||||
<li><b><tt>NE</tt></b>: The emitter count (initially 1)</li>
|
||||
<li><b><tt>AB</tt></b>: The base area in µm²</li>
|
||||
<li><b><tt>PB</tt></b>: The base perimeter in µm</li>
|
||||
<li><b><tt>AC</tt></b>: The collector area in µm²</li>
|
||||
<li><b><tt>PC</tt></b>: The collector perimeter in µm</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
Upon extraction, multi-emitter versions are extracted as multiple devices - one
|
||||
for each emitter area - and NE = 1. Bipolar transistors combine when in parallel.
|
||||
In this case, their emitter parameters AE, PE and NE are added.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In SPICE, BJT3 devices are represented by the "Q" element with the
|
||||
device class name as the model name.
|
||||
The API class is <class_doc href="DeviceClassBJT3"/>.
|
||||
</p>
|
||||
|
||||
<h3>Bipolar transistor with substrate</h3>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt4_schematic.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The four-terminal transistor is an extension of the three-terminal one and
|
||||
offers an additional bulk terminal (S).
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Bipolar transistors with bulk can combine in parallel the same way the three-terminal
|
||||
versions do if their bulk terminals are connected to the same net.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the
|
||||
device class name as the model name.
|
||||
The API class is <class_doc href="DeviceClassBJT4"/>.
|
||||
</p>
|
||||
|
||||
<h2>Device extractors</h2>
|
||||
|
||||
<h3>Resistor extractors (<a href="/about/drc_ref_global.xml#resistor">resistor</a>
|
||||
and <a href="/about/drc_ref_global.xml#resistor_with_bulk">resistor_with_bulk</a>)</h3>
|
||||
|
||||
<p>
|
||||
The resistor extractor assumes a layout which consists of a resistor "wire"
|
||||
and two caps (contacts). The wire is specified with the layer symbol "R",
|
||||
the caps are specified with the layer symbol "C":
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The extractor will compute the resistance from the number of squares
|
||||
and the sheet resistance. The sheet resistance needs to be given
|
||||
when creating the extractor:
|
||||
</p>
|
||||
|
||||
<pre>sheet_rho = 0.5
|
||||
model_name = "RES"
|
||||
extract_devices(resistor(model_name, sheet_rho), { "R" => res_layer, "C" => cap_layer })</pre>
|
||||
|
||||
<p>
|
||||
The plain resistor offers two terminals which it outputs on "tA" and "tB" terminal layers.
|
||||
If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "C" layer.
|
||||
respectively.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_ex_ta.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
For the resistor with bulk, the wire area is output on the "tW" terminal layer as
|
||||
the "W" terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/res_ex_tw.png"/>
|
||||
</p>
|
||||
|
||||
<h3>Capacitor extractors (<a href="/about/drc_ref_global.xml#capacitor">capacitor</a>
|
||||
and <a href="/about/drc_ref_global.xml#capacitor_with_bulk">capacitor_with_bulk</a>)</h3>
|
||||
|
||||
<p>
|
||||
Capacitors are assumed to consist of two "plates" (vertical capacitors).
|
||||
The plates are on layers P1 and P2. The capacitor is extracted from the area where
|
||||
these two layers overlap.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The extractor will compute the capacitance from the area of the
|
||||
overlap and the capacitance per area (F/µm²) value.
|
||||
</p>
|
||||
|
||||
<pre>area_cap = 1.5e-15
|
||||
model_name = "CAP"
|
||||
extract_devices(capacitor(model_name, area_cap), { "P1" => metal1, "P2" => metal2 })</pre>
|
||||
|
||||
<p>
|
||||
The plain capacitor offers two terminals which it outputs on "tA" and "tB" terminal layers.
|
||||
If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "P1" and "P2" layers
|
||||
respectively.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_ex_ta.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
For the capacitor with bulk, the capacitor area is output on the "tW" terminal layer as
|
||||
the "W" terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/cap_ex_tw.png"/>
|
||||
</p>
|
||||
|
||||
<h3>Diode extractor (<a href="/about/drc_ref_global.xml#diode">diode</a>)</h3>
|
||||
|
||||
<p>
|
||||
Diodes are assumed to consist of two vertical implant regions (wells, diffusion).
|
||||
One of the regions is p type ("P" layer) and the other "n" type ("N" layer).
|
||||
These layers also form the anode (p) and cathode (n) of the diode.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/diode_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The extractor will compute the capacitance from the area of the
|
||||
overlap and the capacitance per area (F/µm²) value.
|
||||
</p>
|
||||
|
||||
<pre>model_name = "DIODE"
|
||||
extract_devices(diode(model_name), { "P" => pplus, "N" => nwell })</pre>
|
||||
|
||||
<p>
|
||||
The diode offers two terminals which it outputs on "tA" and "tC" terminal layers.
|
||||
If "tA" is not specified, "A" terminals will be written on the "P" layer.
|
||||
If "tC" is not specified, "C" terminals will be written on the "N" layer.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/diode_ex_ta.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/diode_ex_tc.png"/>
|
||||
</p>
|
||||
|
||||
<h3>MOS transistor extractor (<a href="/about/drc_ref_global.xml#mos3">mos3</a> and <a href="/about/drc_ref_global.xml#mos4">mos4</a>)</h3>
|
||||
|
||||
<p>
|
||||
MOS transistors are recognized by their gate ("G" input) and source/drain ("SD" input) regions.
|
||||
Source and drain needs to be separated from the gate shape. The touching edges of gate and
|
||||
source/drain regions define the width of the device, the perpendicular dimension the gate length.
|
||||
Because the separation of source/drain, the computation of gates and the separation of
|
||||
these for NMOS and PMOS devices, the "G" and "SD" layers are usually derived layers.
|
||||
As these usually won't participate in the connectivity, it's important to specify the
|
||||
"tS", "tD", "tG" and "tB" (for MOS4) layers explicitly and redirect the terminal shapes
|
||||
to layers that really participate in connections.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<pre>model_name = "PMOS"
|
||||
extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" => (active & poly), "W" => nwell,
|
||||
"tS" => active, "tD" => active, "tG" => poly, "tB" => nwell })</pre>
|
||||
|
||||
<p>
|
||||
The MOS3 device produces three terminals which it outputs on "tS", "tG" and "tD" terminal layers (source,
|
||||
gate and drain respectively):
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos_ex_ts.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos_ex_tg.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos_ex_td.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The MOS4 device offers one more terminal (bulk) which it writes on "tB".
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/mos_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<h3>Bipolar transistor extractor (<a href="/about/drc_ref_global.xml#bjt3">bjt3</a> and <a href="/about/drc_ref_global.xml#bjt4">bjt4</a>)</h3>
|
||||
|
||||
<p>
|
||||
There are basically two kind of bipolar transistors: vertical and lateral ones.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Lateral transistors are formed by implant or diffusion wells creating a intermittent
|
||||
n/p structure on the wafer. The basic recognition region is the base region. The collector
|
||||
and emitter regions are inside or overlapping the base region and use the opposite doping
|
||||
than base: if the base region is n doped, then
|
||||
collector and emitter regions have to be p doped. The structure then forms a PNP transistor.
|
||||
KLayout recognizes lateral transistors when the base is <b>partially</b> covered by the collector region.
|
||||
For lateral transistors, the emitter is defined by the emitter region inside base. The
|
||||
collector region is defined by collector inside base and outside emitter.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_lateral.png"/> (lateral PNP transistor)
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors
|
||||
are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed
|
||||
by taking the collector as the substrate, nwell for the base and pplus implant for the emitter.
|
||||
KLayout recognizes a vertical bipolar transistor when the base is covered <b>entirely</b> by the
|
||||
collector or has <b>no collector at all</b> - this means the collector
|
||||
region can be empty (e.g. bulk).
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_vertical.png"/> (vertical PNP transistor)
|
||||
</p>
|
||||
|
||||
<p>
|
||||
In both cases, there can be multiple emitter regions inside a base island. In this
|
||||
case, one transistor is extracted for each emitter region.
|
||||
</p>
|
||||
|
||||
<h4>Vertical bipolar transistors</h4>
|
||||
|
||||
<p>
|
||||
Vertical bipolar transistors take their inputs from "B" (base), "C" (collector)
|
||||
and "E" (emitter). "C" is optional:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Especially for bipolar devices it's important to device useful terminal output
|
||||
layers. Typically, the wells and diffusion areas will be connected through "contact",
|
||||
(not considering the Schottky diodes for now).
|
||||
So it's a good idea to send the terminals to the contact layer:
|
||||
</p>
|
||||
|
||||
<pre>model_name = "PNP"
|
||||
extract_devices(bjt3(model_name), { "C" => collector, "B" => base, "E" => emitter,
|
||||
"tC" => contact, "tB" => contact, "tE" => contact })</pre>
|
||||
|
||||
<p>
|
||||
The BJT3 device produces three terminals which it outputs on "tC", "tB" and "tE" terminal layers (collector,
|
||||
base and emitter respectively):
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_tc.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_te.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
If the collector region is empty (e.g. p substrate), the base shape is copied to the "tC" output layer
|
||||
for the collector terminal.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The BJT4 device offers one more terminal (substrate) which it writes on "tS". "tS" is
|
||||
a copy of the emitter shape but connected to the substrate terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjt_ex_ts.png"/>
|
||||
</p>
|
||||
|
||||
<h4>Lateral bipolar transistors</h4>
|
||||
|
||||
<p>
|
||||
Lateral bipolar transistors also take their inputs from "B" (base), "C" (collector)
|
||||
and "E" (emitter). For lateral transistors, "C" is not optional and must not fully cover
|
||||
the base region. Apart from this, the use model for BJT3 and BJT4 extractors is
|
||||
identical for vertical and lateral transistors.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
A typical lateral transistor is formed by a collector ring and emitter
|
||||
island inside the base region:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_layout.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The terminals produced by the bipolar transistor extractor in the lateral case are
|
||||
the same than for the vertical case, but with a different geometry:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_tc.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_tb.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_te.png"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Again, for BJT4, "tS" is a copy of the emitter shape but connected to the substrate terminal:
|
||||
</p>
|
||||
|
||||
<p>
|
||||
<img src="/manual/bjtlat_ex_ts.png"/>
|
||||
</p>
|
||||
<p>Device extractors are documented here: <link href="/manual/lvs_device_extractors.xml"/>.</p>
|
||||
|
||||
</doc>
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,240 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE language SYSTEM "klayout_doc.dtd">
|
||||
|
||||
<doc>
|
||||
|
||||
<title>LVS Input/Output</title>
|
||||
<keyword name="LVS"/>
|
||||
<keyword name="LVS Input Output"/>
|
||||
<keyword name="LVS SPICE"/>
|
||||
|
||||
<h2-index/>
|
||||
|
||||
<p>
|
||||
LVS (and also DRC as far as netlist extraction is concerned) provides interfaces
|
||||
to write and read netlists/schematics, annotated layout and LVS results.
|
||||
There are three major categories of I/O:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li><b>Netlist</b>: this is the plain circuit information. With subcircuit this
|
||||
forms a hierarchical netlist. Currently, the format available to import and export
|
||||
netlists is a certain SPICE netlist flavor. It's possible to customize the reading
|
||||
and writing process to achieve some flexibility.
|
||||
</li>
|
||||
<li><b>Layout-to-netlist database (L2N DB)</b>: also called extracted netlist or annotated layout.
|
||||
This is the netlist taken from the original layout together with the corresponding shapes.
|
||||
This database allows reconstructing a net geometrically as far as non-device shapes
|
||||
are involved. Devices are abstracted by their terminal geometries.
|
||||
</li>
|
||||
<li><b>LVS result database (LVS DB)</b>: this is the L2N database plus the reference netlist
|
||||
and a "cross reference": a list of paired circuits, nets, devices, pins and subcircuits
|
||||
and status information. The cross-reference is both a lookup table and a debugging
|
||||
aid.
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<h2>Writing netlists</h2>
|
||||
|
||||
<p>
|
||||
You can write a netlist file to supply netlists for (functional) simulators for example.
|
||||
Within LVS scripts, the global "target_netlist" statement triggers writing of a netlist
|
||||
(see <a href="/about/drc_ref_global.xml#target_netlist">target_netlist</a> for details).
|
||||
</p>
|
||||
|
||||
<pre>target_netlist("output.cir", write_spice, "Created by KLayout")</pre>
|
||||
|
||||
<p>
|
||||
This statement can basically appear anywhere in the LVS script. The netlist will
|
||||
written after the script has executed successfully. The first argument is
|
||||
the file's path (by default relative to the original layout file). The second
|
||||
argument is the "writer". "write_spice" creates a netlist writer writing SPICE
|
||||
format with a limited degree of flexbility. See below for customizing the writer.
|
||||
The third argument finally is an (optional) comment which will be written into
|
||||
the netlist as a header.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
The "write_spice" configuration function has two options:
|
||||
</p>
|
||||
|
||||
<pre>write_spice(use_net_names, with_comments)</pre>
|
||||
|
||||
<p>
|
||||
Both options are boolean values. If true and present, the first option will make
|
||||
the writer use the real net's names instead of numerical IDs. If true and present,
|
||||
"with_comments" will embed debug comments into the netlist showing instance
|
||||
locations, pin names etc.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Further customization can be achieved by providing an explicit SPICE writer
|
||||
with a delegate (see <class_doc href="NetlistSpiceWriterDelegate"/>). For
|
||||
doing so, subclass NetlistSpiceWriterDelegate and reimplement one
|
||||
or several of the methods provided for reimplementation. Those are
|
||||
<class_doc href="NetlistSpiceWriterDelegate#write_device"/>,
|
||||
<class_doc href="NetlistSpiceWriterDelegate#write_device_intro"/> and
|
||||
<class_doc href="NetlistSpiceWriterDelegate#write_header"/>.
|
||||
</p>
|
||||
|
||||
<p>
|
||||
Here is an example that supplied subcircuit models rather than
|
||||
device elements:
|
||||
</p>
|
||||
|
||||
<pre># Write extracted netlist to extracted.cir using a special
|
||||
# writer delegate
|
||||
|
||||
# This delegate makes the writer emit subcicuit calls instead of
|
||||
# standard elements for the devices
|
||||
class SubcircuitModels < RBA::NetlistSpiceWriterDelegate
|
||||
|
||||
def write_header
|
||||
emit_line(".INCLUDE 'models.cir'")
|
||||
end
|
||||
|
||||
def write_device(device)
|
||||
str = "X" + device.expanded_name
|
||||
device_class = device.device_class
|
||||
device_class.terminal_definitions.each do |td|
|
||||
str += " " + net_to_string(device.net_for_terminal(td.id))
|
||||
end
|
||||
str += " " + device_class.name
|
||||
str += " PARAMS:"
|
||||
device_class.parameter_definitions.each do |pd|
|
||||
str += " " + pd.name + ("=%.12g" % device.parameter(pd.id))
|
||||
end
|
||||
emit_line(str)
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
# Prepare a writer using the new delegate
|
||||
custom_spice_writer = RBA::NetlistSpiceWriter::new(SubcircuitModels::new)
|
||||
custom_spice_writer.use_net_names= true
|
||||
custom_spice_writer.with_comments = false
|
||||
|
||||
# The declaration of netlist production using the new custom writer
|
||||
target_netlist("extracted.cir", custom_spice_writer, "Extracted by KLayout")</pre>
|
||||
|
||||
<p>
|
||||
This script will produce the following netlist for the simple inverter
|
||||
from the LVS introduction. Instead of printing "M" elements - which is the
|
||||
default - subcircuit calls are produced. This allows putting more elaborate
|
||||
models into subcircuits. The device class name addresses these model
|
||||
subcircuits:
|
||||
</p>
|
||||
|
||||
<pre>* Extracted by KLayout
|
||||
.INCLUDE 'models.cir'
|
||||
|
||||
.SUBCKT INVERTER
|
||||
X$1 VDD IN OUT NWELL PMOS PARAMS: L=0.25 W=1.5 AS=0.675 AD=0.675 PS=3.9 PD=3.9
|
||||
X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.9 AS=0.405 AD=0.405 PS=2.7
|
||||
+ PD=2.7
|
||||
.ENDS INVERTER</pre>
|
||||
|
||||
<p>
|
||||
Netlists can be written directly from the netlist object. Within the script, the
|
||||
netlist object can be obtained with the <a href="/about/_drc_ref_global.xml#netlist">netlist</a> function.
|
||||
This function will first trigger a netlist extraction unless this was done already and
|
||||
return a <class_doc href="Netlist"/> object. Use <class_doc href="Netlist#write"/> to
|
||||
write this netlist object then. Unlike "target_netlist", this method is executed immediately and
|
||||
this way, a single netlist can be written to multiple files in different flavours.
|
||||
</p>
|
||||
|
||||
<h2>Reading netlists</h2>
|
||||
|
||||
<p>
|
||||
The main use case for reading netlists is for comparison in LVS.
|
||||
Reference netlists are read with the "schematic" function
|
||||
(see <a href="/about/drc_ref_global.xml#schematic">schematic</a>):
|
||||
</p>
|
||||
|
||||
<pre>schematic("inverter.cir")</pre>
|
||||
|
||||
<p>
|
||||
Currently SPICE is understood with some limitations:
|
||||
</p>
|
||||
|
||||
<ul>
|
||||
<li>Parametrized circuits are not permitted except for device subcircuits
|
||||
(with a delegate)</li>
|
||||
<li>Only a subset of elements is implemented by default. These are
|
||||
"M" (gives "MOS4" device classes), "Q" (gives BJT3 or BJT4 device
|
||||
classes), "R" (gives Resistor device classes), "C" (gives
|
||||
Capacitor device classes) and "D" (gives diode device classes).</li>
|
||||
</ul>
|
||||
|
||||
<p>
|
||||
As for the SPICE reader, a delegate can be provided to customize the reader.
|
||||
For doing so, subclass the <class_doc href="NetlistSpiceReaderDelegate"/>
|
||||
class and reimplement the methods provided. These are:
|
||||
<class_doc href="NetlistSpiceReaderDelegate#wants_subcircuit"/>,
|
||||
<class_doc href="NetlistSpiceReaderDelegate#element"/>,
|
||||
<class_doc href="NetlistSpiceReaderDelegate#finish"/> and
|
||||
<class_doc href="NetlistSpiceReaderDelegate#start"/>
|
||||
</p>
|
||||
|
||||
<p>
|
||||
This example customizes a reader to pull MOS devices from
|
||||
subcircuit models rather than from "M" elements. Basically this
|
||||
customization does the opposite part of the writer customization
|
||||
before (only for MOS devices).
|
||||
</p>
|
||||
|
||||
<pre># Provides a SPICE netlist reader delegate which turns
|
||||
# some subcircuit models (for subcircuits NMOS and PMOS)
|
||||
# into devices
|
||||
|
||||
class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
|
||||
|
||||
# says we want to catch these subcircuits as devices
|
||||
def wants_subcircuit(name)
|
||||
name == "NMOS" || name == "PMOS"
|
||||
end
|
||||
|
||||
# translate the element
|
||||
def element(circuit, el, name, model, value, nets, params)
|
||||
|
||||
if el != "X"
|
||||
# all other elements are left to the standard implementation
|
||||
return super
|
||||
end
|
||||
|
||||
if nets.size != 4
|
||||
error("Subcircuit #{model} needs four nodes")
|
||||
end
|
||||
|
||||
# provide a device class
|
||||
cls = circuit.netlist.device_class_by_name(model)
|
||||
if ! cls
|
||||
cls = RBA::DeviceClassMOS4Transistor::new
|
||||
cls.name = model
|
||||
circuit.netlist.add(cls)
|
||||
end
|
||||
|
||||
# create a device
|
||||
device = circuit.create_device(cls, name)
|
||||
|
||||
# and configure the device
|
||||
[ "S", "G", "D", "B" ].each_with_index do |t,index|
|
||||
device.connect_terminal(t, nets[index])
|
||||
end
|
||||
params.each do |p,value|
|
||||
device.set_parameter(p, value)
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
# Instantiate a reader using the new delegate
|
||||
reader = RBA::NetlistSpiceReader::new(SubcircuitModelsReader::new)
|
||||
|
||||
# Import the schematic with this reader
|
||||
schematic("inv_xmodels.cir", reader)</pre>
|
||||
|
||||
|
||||
|
||||
</doc>
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE language SYSTEM "klayout_doc.dtd">
|
||||
|
||||
<doc>
|
||||
|
||||
<title>LVS Device Classes</title>
|
||||
<keyword name="LVS"/>
|
||||
<keyword name="LVS Device Classes"/>
|
||||
|
||||
<h2-index/>
|
||||
|
||||
<p>
|
||||
LVS (and also DRC as far as netlist extraction is concerned) provides
|
||||
|
||||
</p>
|
||||
|
||||
</doc>
|
||||
|
|
@ -174,6 +174,11 @@
|
|||
<file alias="lvs_intro.xml">doc/manual/lvs_intro.xml</file>
|
||||
<file alias="lvs_browser.png">doc/manual/lvs_browser.png</file>
|
||||
<file alias="lvs_devices.xml">doc/manual/lvs_devices.xml</file>
|
||||
<file alias="lvs_device_classes.xml">doc/manual/lvs_device_classes.xml</file>
|
||||
<file alias="lvs_device_extractors.xml">doc/manual/lvs_device_extractors.xml</file>
|
||||
<file alias="lvs_io.xml">doc/manual/lvs_io.xml</file>
|
||||
<file alias="lvs_compare.xml">doc/manual/lvs_compare.xml</file>
|
||||
<file alias="lvs_tweaks.xml">doc/manual/lvs_tweaks.xml</file>
|
||||
<file alias="inv.png">doc/manual/inv.png</file>
|
||||
<file alias="inv_no_transistors.png">doc/manual/inv_no_transistors.png</file>
|
||||
<file alias="inv_transistors.png">doc/manual/inv_transistors.png</file>
|
||||
|
|
|
|||
Loading…
Reference in New Issue