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WIP: updated doc.

This commit is contained in:
Matthias Koefferlein 2019-07-03 01:48:55 +02:00
parent 0399b07ff3
commit 437ead7699
4 changed files with 6 additions and 1 deletions
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src/lay/lay/doc/manual/bjt_lateral.png Normal file
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src/lay/lay/doc/manual/bjt_vertical.png
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src/lay/lay/doc/manual/lvs_devices.xml
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@ -447,6 +447,10 @@ extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" =>
collector region is defined by collector inside base and outside emitter.
</p>
<p>
<img src="/manual/bjt_lateral.png"/> (lateral PNP transistor)
</p>
<p>
Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors
are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed
@ -457,7 +461,7 @@ extract_devices(mos4(model_name), { "SD" => (active - poly) &amp; pplus, "G" =>
</p>
<p>
<img src="/manual/bjt_vertical.png"/>
<img src="/manual/bjt_vertical.png"/> (vertical PNP transistor)
</p>
<p>

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src/lay/lay/layHelpResources.qrc
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@ -211,6 +211,7 @@
<file alias="bjt_ex_tb.png">doc/manual/bjt_ex_tb.png</file>
<file alias="bjt_ex_ts.png">doc/manual/bjt_ex_ts.png</file>
<file alias="bjt_vertical.png">doc/manual/bjt_vertical.png</file>
<file alias="bjt_lateral.png">doc/manual/bjt_lateral.png</file>
<file alias="bjtlat_ex_layout.png">doc/manual/bjtlat_ex_layout.png</file>
<file alias="bjtlat_ex_te.png">doc/manual/bjtlat_ex_te.png</file>
<file alias="bjtlat_ex_tc.png">doc/manual/bjtlat_ex_tc.png</file>