mirror of https://github.com/KLayout/klayout.git
Providing LVS tests.
This commit is contained in:
Matthias Koefferlein
parent
95a1e38fe3
commit
bc2d9448d6
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@ -28,64 +28,36 @@
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#include "lymMacro.h"
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#include "tlFileUtils.h"
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#if 0 // @@@
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TEST(1)
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void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout, bool with_l2n = false)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_1.lvs";
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rs += "/testdata/lvs/" + suffix + ".lvs";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au1.gds";
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std::string src = tl::testsrc ();
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src += "/testdata/lvs/" + layout;
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std::string output = this->tmp_file ("tmp.gds");
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std::string au_lvsdb = tl::testsrc ();
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au_lvsdb += "/testdata/lvs/" + suffix + ".lvsdb";
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = nil\n"
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"$lvs_test_target = '%s'\n"
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, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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std::string au_cir = tl::testsrc ();
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au_cir += "/testdata/lvs/" + suffix + ".cir";
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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std::string au_l2n = tl::testsrc ();
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au_l2n += "/testdata/lvs/" + suffix + ".l2n";
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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}
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TEST(2)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_2.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/lvstest.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au2.gds";
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std::string output = this->tmp_file ("tmp.gds");
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std::string output_lvsdb = _this->tmp_file ("tmp.lvsdb");
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std::string output_cir = _this->tmp_file ("tmp.cir");
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std::string output_l2n = _this->tmp_file ("tmp.l2n");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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"$lvs_test_target_lvsdb = '%s'\n"
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"$lvs_test_target_cir = '%s'\n"
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"$lvs_test_target_l2n = '%s'\n"
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, src, output_lvsdb, output_cir, output_l2n)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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@ -95,529 +67,30 @@ TEST(2)
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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_this->compare_text_files (output_lvsdb, au_lvsdb);
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_this->compare_text_files (output_cir, au_cir);
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if (with_l2n) {
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_this->compare_text_files (output_l2n, au_l2n);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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}
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TEST(3_Flat)
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TEST(1_simple)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_3.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/lvstest.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au3.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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run_test (_this, "ringo_simple", "ringo.gds");
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}
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TEST(4_Hierarchical)
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TEST(2_simple_io)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_4.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/lvstest.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au4.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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run_test (_this, "ringo_simple_io", "ringo.gds");
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}
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TEST(5_FlatAntenna)
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TEST(3_simple_io2)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_5.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/antenna_l1.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au5.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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run_test (_this, "ringo_simple_io2", "ringo.gds", true);
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}
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TEST(6_HierarchicalAntenna)
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TEST(4_simple_implicit_connections)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_6.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/antenna_l1.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au6.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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run_test (_this, "ringo_simple_implicit_connections", "ringo_implicit_connections.gds");
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}
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TEST(7_AntennaWithDiodes)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_7.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/antenna_l1.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au7.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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}
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TEST(8_TextsAndPolygons)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_8.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/texts.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au8.gds";
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std::string output = this->tmp_file ("tmp.gds");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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, input, output)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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db::Layout layout;
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{
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tl::InputStream stream (output);
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db::Reader reader (stream);
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reader.read (layout);
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}
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db::compare_layouts (_this, layout, au, db::NoNormalization);
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}
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static void compare_netlists (tl::TestBase *_this, const std::string &cir, const std::string &cir_au)
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{
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db::Netlist nl, nl_au;
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db::NetlistSpiceReader reader;
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{
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tl::info << "Output: " << cir;
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tl::InputStream is (cir);
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reader.read (is, nl);
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}
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{
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tl::info << "Golden: " << cir_au;
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tl::InputStream is (cir_au);
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reader.read (is, nl_au);
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}
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db::compare_netlist (_this, nl, nl_au);
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}
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TEST(9_NetlistExtraction)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_9.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/ringo.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au9a.cir";
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std::string au_simplified = tl::testsrc ();
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au_simplified += "/testdata/lvs/lvsSimpleTests_au9b.cir";
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std::string output = this->tmp_file ("tmp.cir");
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std::string output_simplified = this->tmp_file ("tmp_simplified.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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"$lvs_test_target_simplified = '%s'\n"
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, input, output, output_simplified)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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// verify
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CHECKPOINT ();
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compare_netlists (_this, output, au);
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CHECKPOINT ();
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compare_netlists (_this, output_simplified, au_simplified);
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}
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TEST(10_NetlistExtractionFlat)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_10.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/ringo.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au10a.cir";
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std::string au_simplified = tl::testsrc ();
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au_simplified += "/testdata/lvs/lvsSimpleTests_au10b.cir";
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std::string output = this->tmp_file ("tmp.cir");
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std::string output_simplified = this->tmp_file ("tmp_simplified.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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"$lvs_test_target_simplified = '%s'\n"
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, input, output, output_simplified)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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// verify
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CHECKPOINT ();
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compare_netlists (_this, output, au);
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CHECKPOINT ();
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compare_netlists (_this, output_simplified, au_simplified);
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}
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TEST(11_CustomDevices)
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{
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std::string rs = tl::testsrc ();
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rs += "/testdata/lvs/lvsSimpleTests_11.lvs";
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std::string input = tl::testsrc ();
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input += "/testdata/lvs/vdiv.gds";
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std::string au = tl::testsrc ();
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au += "/testdata/lvs/lvsSimpleTests_au11a.cir";
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std::string au_simplified = tl::testsrc ();
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au_simplified += "/testdata/lvs/lvsSimpleTests_au11b.cir";
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std::string output = this->tmp_file ("tmp.cir");
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std::string output_simplified = this->tmp_file ("tmp_simplified.cir");
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{
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// Set some variables
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lym::Macro config;
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config.set_text (tl::sprintf (
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"$lvs_test_source = '%s'\n"
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"$lvs_test_target = '%s'\n"
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"$lvs_test_target_simplified = '%s'\n"
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, input, output, output_simplified)
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);
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config.set_interpreter (lym::Macro::Ruby);
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EXPECT_EQ (config.run (), 0);
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}
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lym::Macro lvs;
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lvs.load_from (rs);
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EXPECT_EQ (lvs.run (), 0);
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// verify
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CHECKPOINT ();
|
||||
compare_netlists (_this, output, au);
|
||||
|
||||
CHECKPOINT ();
|
||||
compare_netlists (_this, output_simplified, au_simplified);
|
||||
}
|
||||
|
||||
TEST(12_NetlistJoinLabels)
|
||||
{
|
||||
std::string rs = tl::testsrc ();
|
||||
rs += "/testdata/lvs/lvsSimpleTests_12.lvs";
|
||||
|
||||
std::string input = tl::testsrc ();
|
||||
input += "/testdata/lvs/implicit_nets.gds";
|
||||
|
||||
std::string au = tl::testsrc ();
|
||||
au += "/testdata/lvs/lvsSimpleTests_au12a.cir";
|
||||
|
||||
std::string output = this->tmp_file ("tmp.cir");
|
||||
|
||||
{
|
||||
// Set some variables
|
||||
lym::Macro config;
|
||||
config.set_text (tl::sprintf (
|
||||
"$lvs_test_source = '%s'\n"
|
||||
"$lvs_test_target = '%s'\n"
|
||||
"$lvs_test_target_simplified = nil\n"
|
||||
, input, output)
|
||||
);
|
||||
config.set_interpreter (lym::Macro::Ruby);
|
||||
EXPECT_EQ (config.run (), 0);
|
||||
}
|
||||
|
||||
lym::Macro lvs;
|
||||
lvs.load_from (rs);
|
||||
EXPECT_EQ (lvs.run (), 0);
|
||||
|
||||
// verify
|
||||
|
||||
CHECKPOINT ();
|
||||
compare_netlists (_this, output, au);
|
||||
}
|
||||
|
||||
TEST(13a_KissingCorners)
|
||||
{
|
||||
std::string rs = tl::testsrc ();
|
||||
rs += "/testdata/lvs/lvsSimpleTests_13a.lvs";
|
||||
|
||||
std::string input = tl::testsrc ();
|
||||
input += "/testdata/lvs/kissing_corners.gds";
|
||||
|
||||
std::string au = tl::testsrc ();
|
||||
au += "/testdata/lvs/lvsSimpleTests_au13a.gds";
|
||||
|
||||
std::string output = this->tmp_file ("tmp.gds");
|
||||
|
||||
{
|
||||
// Set some variables
|
||||
lym::Macro config;
|
||||
config.set_text (tl::sprintf (
|
||||
"$lvs_test_source = '%s'\n"
|
||||
"$lvs_test_target = '%s'\n"
|
||||
, input, output)
|
||||
);
|
||||
config.set_interpreter (lym::Macro::Ruby);
|
||||
EXPECT_EQ (config.run (), 0);
|
||||
}
|
||||
|
||||
lym::Macro lvs;
|
||||
lvs.load_from (rs);
|
||||
EXPECT_EQ (lvs.run (), 0);
|
||||
|
||||
// verify
|
||||
|
||||
db::Layout layout;
|
||||
|
||||
{
|
||||
tl::InputStream stream (output);
|
||||
db::Reader reader (stream);
|
||||
reader.read (layout);
|
||||
}
|
||||
|
||||
CHECKPOINT ();
|
||||
db::compare_layouts (_this, layout, au, db::NoNormalization);
|
||||
}
|
||||
|
||||
TEST(13b_KissingCornersDeep)
|
||||
{
|
||||
std::string rs = tl::testsrc ();
|
||||
rs += "/testdata/lvs/lvsSimpleTests_13b.lvs";
|
||||
|
||||
std::string input = tl::testsrc ();
|
||||
input += "/testdata/lvs/kissing_corners.gds";
|
||||
|
||||
std::string au = tl::testsrc ();
|
||||
au += "/testdata/lvs/lvsSimpleTests_au13b.gds";
|
||||
|
||||
std::string output = this->tmp_file ("tmp.gds");
|
||||
|
||||
{
|
||||
// Set some variables
|
||||
lym::Macro config;
|
||||
config.set_text (tl::sprintf (
|
||||
"$lvs_test_source = '%s'\n"
|
||||
"$lvs_test_target = '%s'\n"
|
||||
, input, output)
|
||||
);
|
||||
config.set_interpreter (lym::Macro::Ruby);
|
||||
EXPECT_EQ (config.run (), 0);
|
||||
}
|
||||
|
||||
lym::Macro lvs;
|
||||
lvs.load_from (rs);
|
||||
EXPECT_EQ (lvs.run (), 0);
|
||||
|
||||
// verify
|
||||
|
||||
db::Layout layout;
|
||||
|
||||
{
|
||||
tl::InputStream stream (output);
|
||||
db::Reader reader (stream);
|
||||
reader.read (layout);
|
||||
}
|
||||
|
||||
CHECKPOINT ();
|
||||
db::compare_layouts (_this, layout, au, db::NoNormalization);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
|
||||
.SUBCKT RINGO VSS VDD FB ENABLE OUT
|
||||
X$1 VDD 1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD 2 VSS VDD 1 VSS INVX1
|
||||
X$3 VDD 3 VSS VDD 2 VSS INVX1
|
||||
X$4 VDD 4 VSS VDD 3 VSS INVX1
|
||||
X$5 VDD 5 VSS VDD 4 VSS INVX1
|
||||
X$6 VDD 6 VSS VDD 5 VSS INVX1
|
||||
X$7 VDD 7 VSS VDD 6 VSS INVX1
|
||||
X$8 VDD 8 VSS VDD 7 VSS INVX1
|
||||
X$9 VDD 9 VSS VDD 8 VSS INVX1
|
||||
X$10 VDD 10 VSS VDD 9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD 10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
|
||||
M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U
|
||||
M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U
|
||||
M$4 1 B OUT BULK NMOS L=0.25U W=0.95U
|
||||
.ENDS ND2X1
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK
|
||||
M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U
|
||||
.ENDS INVX1
|
||||
Binary file not shown.
Binary file not shown.
|
|
@ -0,0 +1,83 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VSS
|
||||
.SUBCKT RINGO 11 12 13 14 15
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 13 OUT
|
||||
* net 14 ENABLE
|
||||
* net 15 VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 15 12 11 14 15 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 15 12 1 15 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 15 12 2 15 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 15 12 3 15 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 15 12 4 15 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 15 12 5 15 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 15 12 6 15 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 15 12 7 15 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 15 12 8 15 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 15 12 9 15 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 15 12 10 15 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 13 15 12 11 15 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
|
|
@ -0,0 +1,962 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-2550 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VSS
|
||||
.SUBCKT RINGO 11 12 13 14 15
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 13 OUT
|
||||
* net 14 ENABLE
|
||||
* net 15 VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 15 12 11 14 15 ND2X1
|
||||
* cell instance $2 r0 *1 4.7,0
|
||||
X$2 12 2 15 12 1 15 INVX1
|
||||
* cell instance $3 r0 *1 6.5,0
|
||||
X$3 12 3 15 12 2 15 INVX1
|
||||
* cell instance $4 r0 *1 8.3,0
|
||||
X$4 12 4 15 12 3 15 INVX1
|
||||
* cell instance $5 r0 *1 10.1,0
|
||||
X$5 12 5 15 12 4 15 INVX1
|
||||
* cell instance $6 r0 *1 11.9,0
|
||||
X$6 12 6 15 12 5 15 INVX1
|
||||
* cell instance $7 r0 *1 13.7,0
|
||||
X$7 12 7 15 12 6 15 INVX1
|
||||
* cell instance $8 r0 *1 15.5,0
|
||||
X$8 12 8 15 12 7 15 INVX1
|
||||
* cell instance $9 r0 *1 17.3,0
|
||||
X$9 12 9 15 12 8 15 INVX1
|
||||
* cell instance $10 r0 *1 19.1,0
|
||||
X$10 12 10 15 12 9 15 INVX1
|
||||
* cell instance $11 r0 *1 20.9,0
|
||||
X$11 12 11 15 12 10 15 INVX1
|
||||
* cell instance $12 r0 *1 24.7,0
|
||||
X$12 12 13 15 12 11 15 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Implicit
|
||||
connect_implicit("VSS")
|
||||
connect_implicit("VDD")
|
||||
|
||||
# Compare section
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
|
|
@ -0,0 +1,981 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (5210 3010) (180 180))
|
||||
rect(l11 (-1350 -240) (1160 300))
|
||||
rect(l1 (-3100 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (7010 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8810 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10610 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (12410 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (14210 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (16010 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17810 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19610 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (21410 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (25210 3010) (180 180))
|
||||
rect(l8 (-22200 720) (180 180))
|
||||
rect(l11 (18880 -1140) (2900 300))
|
||||
rect(l11 (-21980 590) (320 320))
|
||||
rect(l11 (18570 -320) (320 320))
|
||||
rect(l12 (-19150 -260) (200 200))
|
||||
rect(l12 (18690 -200) (200 200))
|
||||
rect(l13 (-18840 -300) (18890 400))
|
||||
rect(l13 (-19071 -201) (2 2))
|
||||
rect(l13 (-171 -201) (400 400))
|
||||
rect(l13 (18490 -400) (400 400))
|
||||
rect(l1 (-545 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (22600 4500) (1400 3500))
|
||||
rect(l3 (-23500 -3500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (25800 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-5090 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-22280 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (25720 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-4891 1009) (2 2))
|
||||
rect(l11 (2798 -52) (2 2))
|
||||
rect(l11 (-22152 -102) (2 2))
|
||||
rect(l11 (19749 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-22751 -401) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (25900 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23300 -2550) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (-18850 -1500) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (21775 -1500) (425 1500))
|
||||
rect(l9 (-2375 -450) (500 1500))
|
||||
rect(l9 (-22600 -1500) (500 1500))
|
||||
rect(l9 (25400 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (25990 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-151 -101) (2 2))
|
||||
rect(l13 (-151 -201) (400 400))
|
||||
rect(l1 (-675 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-200 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-151 -101) (2 2))
|
||||
rect(l13 (-151 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (27010 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-3980 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-22280 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (24709 -291) (2 2))
|
||||
rect(l11 (-3852 -2) (2 2))
|
||||
rect(l11 (-19202 -102) (2 2))
|
||||
rect(l11 (23999 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l11 (-5150 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-22301 -351) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l5 (24400 460) (425 950))
|
||||
rect(l5 (-20425 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (-19525 -950) (425 950))
|
||||
rect(l10 (24325 -2210) (500 1500))
|
||||
rect(l10 (-4300 -1500) (500 1500))
|
||||
rect(l10 (-22600 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4700 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6500 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(8300 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(10100 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11900 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13700 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15500 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(17300 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(19100 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20900 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(24700 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I3 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb)
|
||||
|
||||
writer = write_spice(true, false)
|
||||
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
|
|
@ -0,0 +1,962 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-2550 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
* Extracted by KLayout
|
||||
.INCLUDE 'models.cir'
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
X$1 VDD IN OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.6375 PS=3.85 PD=3.85
|
||||
X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.40375
|
||||
+ PS=2.75 PD=2.75
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
X$1 OUT A VDD \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.3375 PS=3.85 PD=1.95
|
||||
X$2 VDD B OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.3375 AD=0.6375 PS=1.95 PD=3.85
|
||||
X$3 VSS A \$I3 SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.21375
|
||||
+ PS=2.75 PD=1.4
|
||||
X$4 \$I3 B OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.21375 AD=0.40375
|
||||
+ PS=1.4 PD=2.75
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
#%l2n-klayout
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-2550 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb)
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
|
||||
# Write extracted netlist to extracted.cir using a special
|
||||
# writer delegate
|
||||
|
||||
# This delegate makes the writer emit subcicuit calls instead of
|
||||
# standard elements for the devices
|
||||
class SubcircuitModels < RBA::NetlistSpiceWriterDelegate
|
||||
|
||||
def write_header
|
||||
emit_line(".INCLUDE 'models.cir'")
|
||||
end
|
||||
|
||||
def write_device(device)
|
||||
str = "X" + device.expanded_name
|
||||
device_class = device.device_class
|
||||
device_class.terminal_definitions.each do |td|
|
||||
str += " " + net_to_string(device.net_for_terminal(td.id))
|
||||
end
|
||||
str += " " + device_class.name
|
||||
str += " PARAMS:"
|
||||
device_class.parameter_definitions.each do |pd|
|
||||
str += " " + pd.name + ("=%.12g" % device.parameter(pd.id))
|
||||
end
|
||||
emit_line(str)
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
# Prepare a writer using the new delegate
|
||||
custom_spice_writer = RBA::NetlistSpiceWriter::new(SubcircuitModels::new)
|
||||
custom_spice_writer.use_net_names= true
|
||||
custom_spice_writer.with_comments = false
|
||||
|
||||
# The declaration of netlist production using the new custom writer
|
||||
target_netlist($lvs_test_target_cir, custom_spice_writer, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo.cir")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
|
|
@ -0,0 +1,962 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-2550 1800) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue