mirror of https://github.com/KLayout/klayout.git
Matthias Köfferlein
GitHub
commit
fbb8a432c4
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@ -786,7 +786,7 @@ private:
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* @brief Compares edges as "less"
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* Edge comparison is based on the pins attached (name of the first pin).
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*/
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static bool edge_less (const db::Net *a, const db::Net *b);
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static bool net_less (const db::Net *a, const db::Net *b);
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/**
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* @brief Compares edges as "equal"
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@ -1260,8 +1260,8 @@ NetGraphNode::operator< (const NetGraphNode &node) const
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}
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}
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if (m_edges.empty ()) {
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// do a more detailed analysis on the edges
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return edge_less (net (), node.net ());
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// do a more detailed analysis on the nets involved
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return net_less (net (), node.net ());
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}
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return false;
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}
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@ -1285,7 +1285,7 @@ NetGraphNode::operator== (const NetGraphNode &node) const
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}
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bool
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NetGraphNode::edge_less (const db::Net *a, const db::Net *b)
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NetGraphNode::net_less (const db::Net *a, const db::Net *b)
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{
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if ((a != 0) != (b != 0)) {
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return (a != 0) < (b != 0);
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@ -2018,6 +2018,11 @@ NetlistComparer::NetlistComparer (NetlistCompareLogger *logger)
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m_max_n_branch = 100;
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}
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NetlistComparer::~NetlistComparer ()
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{
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// .. nothing yet ..
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}
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void
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NetlistComparer::exclude_caps (double threshold)
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{
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@ -147,6 +147,11 @@ public:
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* "a" is null if there is no match for b and vice versa.
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*/
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virtual void subcircuit_mismatch (const db::SubCircuit * /*a*/, const db::SubCircuit * /*b*/) { }
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private:
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// No copying
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NetlistCompareLogger (const NetlistCompareLogger &);
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NetlistCompareLogger &operator= (const NetlistCompareLogger &);
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};
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/**
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@ -160,6 +165,11 @@ public:
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*/
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NetlistComparer (NetlistCompareLogger *logger = 0);
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/**
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* @brief Destructor
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*/
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~NetlistComparer ();
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/**
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* @brief Mark two nets as identical
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*
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@ -266,6 +276,11 @@ public:
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*/
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bool compare (const db::Netlist *a, const db::Netlist *b, db::NetlistCompareLogger *logger) const;
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private:
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// No copying
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NetlistComparer (const NetlistComparer &);
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NetlistComparer &operator= (const NetlistComparer &);
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protected:
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bool compare_circuits (const db::Circuit *c1, const db::Circuit *c2, db::DeviceCategorizer &device_categorizer, db::CircuitCategorizer &circuit_categorizer, db::CircuitPinMapper &circuit_pin_mapper, const std::vector<std::pair<const Net *, const Net *> > &net_identity, bool &pin_mismatch, std::map<const db::Circuit *, CircuitMapper> &c12_circuit_and_pin_mapping, std::map<const db::Circuit *, CircuitMapper> &c22_circuit_and_pin_mapping) const;
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bool all_subcircuits_verified (const db::Circuit *c, const std::set<const db::Circuit *> &verified_circuits) const;
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@ -294,6 +309,12 @@ template<> struct type_traits<db::NetlistComparer> : public tl::type_traits<void
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typedef tl::false_tag has_default_constructor;
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};
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template<> struct type_traits<db::NetlistCompareLogger> : public tl::type_traits<void>
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{
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// mark "NetlistDeviceExtractor" as having a default ctor and no copy ctor
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typedef tl::false_tag has_copy_constructor;
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};
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}
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#endif
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@ -269,6 +269,10 @@ public:
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}
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private:
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// No copying
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NetlistCrossReference (const db::NetlistCrossReference &);
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NetlistCrossReference &operator= (const db::NetlistCrossReference &);
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tl::weak_ptr<db::Netlist> mp_netlist_a, mp_netlist_b;
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std::vector<std::pair<const db::Circuit *, const db::Circuit *> > m_circuits;
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std::list<PerCircuitData> m_per_circuit_data;
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@ -296,4 +300,15 @@ private:
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}
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namespace tl
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{
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template<> struct type_traits<db::NetlistCrossReference> : public tl::type_traits<void>
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{
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// mark "NetlistDeviceExtractor" as having a default ctor and no copy ctor
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typedef tl::false_tag has_copy_constructor;
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};
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}
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#endif
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@ -106,7 +106,7 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const
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os << "C";
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os << format_name (dev.expanded_name ());
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os << format_terminals (dev);
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os << format_terminals (dev, size_t (2));
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os << " ";
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os << tl::sprintf ("%.12g", dev.parameter_value (db::DeviceClassCapacitor::param_id_C));
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@ -114,7 +114,7 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const
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os << "L";
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os << format_name (dev.expanded_name ());
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os << format_terminals (dev);
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os << format_terminals (dev, size_t (2));
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os << " ";
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os << tl::sprintf ("%.12g", dev.parameter_value (db::DeviceClassInductor::param_id_L));
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@ -122,7 +122,7 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const
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os << "R";
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os << format_name (dev.expanded_name ());
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os << format_terminals (dev);
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os << format_terminals (dev, size_t (2));
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os << " ";
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os << tl::sprintf ("%.12g", dev.parameter_value (db::DeviceClassResistor::param_id_R));
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@ -180,12 +180,13 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const
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emit_line (os.str ());
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}
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std::string NetlistSpiceWriterDelegate::format_terminals (const db::Device &dev) const
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std::string NetlistSpiceWriterDelegate::format_terminals (const db::Device &dev, size_t nmax) const
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{
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std::ostringstream os;
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const std::vector<db::DeviceTerminalDefinition> &td = dev.device_class ()->terminal_definitions ();
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for (std::vector<db::DeviceTerminalDefinition>::const_iterator i = td.begin (); i != td.end (); ++i) {
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size_t n = 0;
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for (std::vector<db::DeviceTerminalDefinition>::const_iterator i = td.begin (); i != td.end () && n < nmax; ++i, ++n) {
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os << " " << net_to_string (dev.net_for_terminal (i->id ()));
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}
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@ -62,7 +62,7 @@ public:
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void emit_line (const std::string &line) const;
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void emit_comment (const std::string &comment) const;
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std::string format_name (const std::string &s) const;
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std::string format_terminals (const db::Device &dev) const;
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std::string format_terminals (const db::Device &dev, size_t max_terminals = std::numeric_limits<size_t>::max ()) const;
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std::string format_params (const db::Device &dev, size_t without_id = std::numeric_limits<size_t>::max ()) const;
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private:
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@ -308,10 +308,19 @@ public:
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gsi::Callback cb_pin_mismatch;
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gsi::Callback cb_match_subcircuits;
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gsi::Callback cb_subcircuit_mismatch;
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private:
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GenericNetlistCompareLogger (const GenericNetlistCompareLogger &d);
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GenericNetlistCompareLogger &operator= (const GenericNetlistCompareLogger &d);
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};
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}
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namespace tl
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{
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template<> struct type_traits<GenericNetlistCompareLogger> : public tl::type_traits<db::NetlistCompareLogger> { };
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}
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namespace gsi
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{
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@ -53,14 +53,7 @@ TEST(1_ReaderBasic)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au.txt");
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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compare_text_files (path, au_path);
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// test build_all_nets from read l2n
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@ -270,15 +263,7 @@ TEST(1b_ReaderBasicShort)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_s.txt");
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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compare_text_files (path, au_path);
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}
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TEST(2_ReaderWithGlobalNets)
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@ -302,14 +287,7 @@ TEST(2_ReaderWithGlobalNets)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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compare_text_files (path, au_path);
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// test build_all_nets from read l2n
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@ -366,14 +344,7 @@ TEST(3_ReaderAbsoluteCoordinates)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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compare_text_files (path, au_path);
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// test build_all_nets from read l2n
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@ -432,14 +403,7 @@ TEST(4_ReaderCombinedDevices)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_reader_au_4.l2n");
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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compare_text_files (path, au_path);
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// test build_all_nets from read l2n
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@ -176,16 +176,7 @@ TEST(1_WriterBasic)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au.txt");
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{
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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}
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compare_text_files (path, au_path);
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path = tmp_file ("tmp_l2nwriter_1s.txt");
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{
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@ -196,16 +187,7 @@ TEST(1_WriterBasic)
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au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_s.txt");
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{
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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}
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compare_text_files (path, au_path);
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// test build_all_nets (verify reference for reader)
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@ -398,16 +380,7 @@ TEST(2_WriterWithGlobalNets)
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2.txt");
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{
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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}
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compare_text_files (path, au_path);
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path = tmp_file ("tmp_l2nwriter_2s.txt");
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{
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@ -418,16 +391,7 @@ TEST(2_WriterWithGlobalNets)
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au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "l2n_writer_au_2s.txt");
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{
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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if (is.read_all () != is_au.read_all ()) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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}
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compare_text_files (path, au_path);
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// test build_all_nets as reference for the reader
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@ -40,13 +40,6 @@
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#include <memory>
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#include <limits>
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#if defined(_MSC_VER)
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// different hash algorithm
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# define AUFILE_SUFFIX ".2"
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#else
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# define AUFILE_SUFFIX ""
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#endif
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static unsigned int define_layer (db::Layout &ly, db::LayerMap &lmap, int gds_layer, int gds_datatype = 0)
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{
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unsigned int lid = ly.insert_layer (db::LayerProperties (gds_layer, gds_datatype));
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@ -56,17 +49,7 @@ static unsigned int define_layer (db::Layout &ly, db::LayerMap &lmap, int gds_la
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static void compare_lvsdbs (tl::TestBase *_this, const std::string &path, const std::string &au_path)
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{
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tl::InputStream is (path);
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tl::InputStream is_au (au_path);
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std::string netlist = is.read_all ();
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std::string netlist_au = is_au.read_all ();
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if (netlist != netlist_au) {
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_this->raise (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s",
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tl::absolute_file_path (path),
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tl::absolute_file_path (au_path)));
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}
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_this->compare_text_files (path, au_path);
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}
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TEST(1_BasicFlow)
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@ -249,7 +232,7 @@ TEST(1_BasicFlow)
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std::string path = tmp_file ("tmp_lvstest1.lvsdb");
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lvs.save (path, false);
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1_au.lvsdb" AUFILE_SUFFIX);
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1_au.lvsdb");
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compare_lvsdbs (_this, path, au_path);
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@ -261,7 +244,7 @@ TEST(1_BasicFlow)
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lvs2.load (path);
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lvs2.save (path2, false);
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std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1b_au.lvsdb" AUFILE_SUFFIX);
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std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test1b_au.lvsdb");
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compare_lvsdbs (_this, path2, au_path2);
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}
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@ -447,7 +430,7 @@ TEST(2_FlowWithErrors)
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std::string path = tmp_file ("tmp_lvstest2.lvsdb");
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lvs.save (path, false);
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2_au.lvsdb" AUFILE_SUFFIX);
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std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2_au.lvsdb");
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compare_lvsdbs (_this, path, au_path);
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|
||||
|
|
@ -459,7 +442,7 @@ TEST(2_FlowWithErrors)
|
|||
lvs2.load (path);
|
||||
lvs2.save (path2, false);
|
||||
|
||||
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2b_au.lvsdb" AUFILE_SUFFIX);
|
||||
std::string au_path2 = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "lvs_test2b_au.lvsdb");
|
||||
|
||||
compare_lvsdbs (_this, path2, au_path2);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -39,8 +39,10 @@ static void compare_netlists (tl::TestBase *_this, const std::string &path, cons
|
|||
std::string netlist_au = is_au.read_all ();
|
||||
|
||||
// normalize "1.0e-005" to "1.0e-05" for compatibility
|
||||
netlist = tl::replaced (netlist, "\r\n", "\n"); // for Windows
|
||||
netlist = tl::replaced (netlist, "e-00", "e-0");
|
||||
netlist = tl::replaced (netlist, "e-0", "e-");
|
||||
netlist_au = tl::replaced (netlist_au, "\r\n", "\n"); // for Windows
|
||||
netlist_au = tl::replaced (netlist_au, "e-00", "e-0");
|
||||
netlist_au = tl::replaced (netlist_au, "e-0", "e-");
|
||||
|
||||
|
|
@ -56,25 +58,9 @@ TEST(1_WriterResistorDevices)
|
|||
db::Netlist nl;
|
||||
|
||||
db::DeviceClass *rcls = new db::DeviceClassResistor ();
|
||||
db::DeviceClass *ccls = new db::DeviceClassCapacitor ();
|
||||
db::DeviceClass *lcls = new db::DeviceClassInductor ();
|
||||
db::DeviceClass *dcls = new db::DeviceClassDiode ();
|
||||
db::DeviceClass *m3cls = new db::DeviceClassMOS3Transistor ();
|
||||
db::DeviceClass *m4cls = new db::DeviceClassMOS4Transistor ();
|
||||
|
||||
rcls->set_name ("RCLS");
|
||||
lcls->set_name ("LCLS");
|
||||
ccls->set_name ("CCLS");
|
||||
dcls->set_name ("DCLS");
|
||||
m3cls->set_name ("M3CLS");
|
||||
m4cls->set_name ("M4CLS");
|
||||
|
||||
nl.add_device_class (rcls);
|
||||
nl.add_device_class (lcls);
|
||||
nl.add_device_class (ccls);
|
||||
nl.add_device_class (dcls);
|
||||
nl.add_device_class (m3cls);
|
||||
nl.add_device_class (m4cls);
|
||||
|
||||
db::Circuit *circuit1 = new db::Circuit ();
|
||||
circuit1->set_name ("C1");
|
||||
|
|
@ -123,30 +109,73 @@ TEST(1_WriterResistorDevices)
|
|||
compare_netlists (_this, path, au_path);
|
||||
}
|
||||
|
||||
TEST(1_WriterResistorDevicesWithBulk)
|
||||
{
|
||||
db::Netlist nl;
|
||||
|
||||
db::DeviceClass *rcls = new db::DeviceClassResistorWithBulk ();
|
||||
rcls->set_name ("RCLS");
|
||||
|
||||
nl.add_device_class (rcls);
|
||||
|
||||
db::Circuit *circuit1 = new db::Circuit ();
|
||||
circuit1->set_name ("C1");
|
||||
nl.add_circuit (circuit1);
|
||||
|
||||
db::Net *n1, *n2, *n3;
|
||||
n1 = new db::Net ();
|
||||
n1->set_name ("n1");
|
||||
circuit1->add_net (n1);
|
||||
n2 = new db::Net ();
|
||||
n2->set_name ("n2");
|
||||
circuit1->add_net (n2);
|
||||
n3 = new db::Net ();
|
||||
n3->set_name ("n3");
|
||||
circuit1->add_net (n3);
|
||||
|
||||
db::Device *rdev1 = new db::Device (rcls);
|
||||
rdev1->set_parameter_value (db::DeviceClassResistor::param_id_R, 1.7);
|
||||
db::Device *rdev2 = new db::Device (rcls);
|
||||
rdev2->set_parameter_value (db::DeviceClassResistor::param_id_R, 42e-6);
|
||||
circuit1->add_device (rdev1);
|
||||
circuit1->add_device (rdev2);
|
||||
|
||||
size_t pid1 = circuit1->add_pin ("p1").id ();
|
||||
size_t pid2 = circuit1->add_pin ("p2").id ();
|
||||
|
||||
circuit1->connect_pin (pid1, n1);
|
||||
circuit1->connect_pin (pid2, n2);
|
||||
|
||||
rdev1->connect_terminal (rdev1->device_class ()->terminal_id_for_name ("A"), n1);
|
||||
rdev1->connect_terminal (rdev1->device_class ()->terminal_id_for_name ("B"), n3);
|
||||
rdev1->connect_terminal (rdev1->device_class ()->terminal_id_for_name ("W"), n3);
|
||||
rdev2->connect_terminal (rdev2->device_class ()->terminal_id_for_name ("A"), n3);
|
||||
rdev2->connect_terminal (rdev2->device_class ()->terminal_id_for_name ("B"), n2);
|
||||
rdev2->connect_terminal (rdev2->device_class ()->terminal_id_for_name ("W"), n3);
|
||||
|
||||
// verify against the input
|
||||
|
||||
std::string path = tmp_file ("tmp_nwriter1.txt");
|
||||
{
|
||||
tl::OutputStream stream (path);
|
||||
db::NetlistSpiceWriter writer;
|
||||
writer.write (stream, nl, "written by unit test");
|
||||
}
|
||||
|
||||
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nwriter1_au.txt");
|
||||
|
||||
compare_netlists (_this, path, au_path);
|
||||
}
|
||||
|
||||
TEST(2_WriterCapacitorDevices)
|
||||
{
|
||||
db::Netlist nl;
|
||||
|
||||
db::DeviceClass *rcls = new db::DeviceClassResistor ();
|
||||
db::DeviceClass *ccls = new db::DeviceClassCapacitor ();
|
||||
db::DeviceClass *lcls = new db::DeviceClassInductor ();
|
||||
db::DeviceClass *dcls = new db::DeviceClassDiode ();
|
||||
db::DeviceClass *m3cls = new db::DeviceClassMOS3Transistor ();
|
||||
db::DeviceClass *m4cls = new db::DeviceClassMOS4Transistor ();
|
||||
|
||||
rcls->set_name ("RCLS");
|
||||
lcls->set_name ("LCLS");
|
||||
ccls->set_name ("CCLS");
|
||||
dcls->set_name ("DCLS");
|
||||
m3cls->set_name ("M3CLS");
|
||||
m4cls->set_name ("M4CLS");
|
||||
|
||||
nl.add_device_class (rcls);
|
||||
nl.add_device_class (lcls);
|
||||
nl.add_device_class (ccls);
|
||||
nl.add_device_class (dcls);
|
||||
nl.add_device_class (m3cls);
|
||||
nl.add_device_class (m4cls);
|
||||
|
||||
db::Circuit *circuit1 = new db::Circuit ();
|
||||
circuit1->set_name ("C1");
|
||||
|
|
@ -195,6 +224,65 @@ TEST(2_WriterCapacitorDevices)
|
|||
compare_netlists (_this, path, au_path);
|
||||
}
|
||||
|
||||
TEST(2_WriterCapacitorDevicesWithBulk)
|
||||
{
|
||||
db::Netlist nl;
|
||||
|
||||
db::DeviceClass *ccls = new db::DeviceClassCapacitorWithBulk ();
|
||||
|
||||
ccls->set_name ("CCLS");
|
||||
|
||||
nl.add_device_class (ccls);
|
||||
|
||||
db::Circuit *circuit1 = new db::Circuit ();
|
||||
circuit1->set_name ("C1");
|
||||
nl.add_circuit (circuit1);
|
||||
|
||||
db::Net *n1, *n2, *n3;
|
||||
n1 = new db::Net ();
|
||||
n1->set_name ("n1");
|
||||
circuit1->add_net (n1);
|
||||
n2 = new db::Net ();
|
||||
n2->set_name ("n2");
|
||||
circuit1->add_net (n2);
|
||||
n3 = new db::Net ();
|
||||
n3->set_name ("n3");
|
||||
circuit1->add_net (n3);
|
||||
|
||||
db::Device *cdev1 = new db::Device (ccls);
|
||||
cdev1->set_parameter_value (db::DeviceClassCapacitor::param_id_C, 1.7e-12);
|
||||
db::Device *cdev2 = new db::Device (ccls);
|
||||
cdev2->set_parameter_value (db::DeviceClassCapacitor::param_id_C, 42e-15);
|
||||
circuit1->add_device (cdev1);
|
||||
circuit1->add_device (cdev2);
|
||||
|
||||
size_t pid1 = circuit1->add_pin ("p1").id ();
|
||||
size_t pid2 = circuit1->add_pin ("p2").id ();
|
||||
|
||||
circuit1->connect_pin (pid1, n1);
|
||||
circuit1->connect_pin (pid2, n2);
|
||||
|
||||
cdev1->connect_terminal (cdev1->device_class ()->terminal_id_for_name ("A"), n1);
|
||||
cdev1->connect_terminal (cdev1->device_class ()->terminal_id_for_name ("B"), n3);
|
||||
cdev1->connect_terminal (cdev1->device_class ()->terminal_id_for_name ("W"), n3);
|
||||
cdev2->connect_terminal (cdev2->device_class ()->terminal_id_for_name ("A"), n3);
|
||||
cdev2->connect_terminal (cdev2->device_class ()->terminal_id_for_name ("B"), n2);
|
||||
cdev2->connect_terminal (cdev2->device_class ()->terminal_id_for_name ("W"), n3);
|
||||
|
||||
// verify against the input
|
||||
|
||||
std::string path = tmp_file ("tmp_nwriter2.txt");
|
||||
{
|
||||
tl::OutputStream stream (path);
|
||||
db::NetlistSpiceWriter writer;
|
||||
writer.write (stream, nl, "written by unit test");
|
||||
}
|
||||
|
||||
std::string au_path = tl::combine_path (tl::combine_path (tl::combine_path (tl::testsrc (), "testdata"), "algo"), "nwriter2_au.txt");
|
||||
|
||||
compare_netlists (_this, path, au_path);
|
||||
}
|
||||
|
||||
TEST(3_WriterInductorDevices)
|
||||
{
|
||||
db::Netlist nl;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
# $autorun-early
|
||||
|
||||
require 'pathname'
|
||||
|
||||
module DRC
|
||||
|
||||
# The DRC engine
|
||||
|
|
@ -1335,126 +1337,135 @@ CODE
|
|||
|
||||
def _finish(final = true)
|
||||
|
||||
_flush
|
||||
|
||||
view = RBA::LayoutView::current
|
||||
begin
|
||||
|
||||
# save the report database if requested
|
||||
if @output_rdb_file
|
||||
rdb_file = _make_path(@output_rdb_file)
|
||||
info("Writing report database: #{rdb_file} ..")
|
||||
@output_rdb.save(rdb_file)
|
||||
end
|
||||
if @output_rdb && final && view
|
||||
view.show_rdb(@output_rdb_index, view.active_cellview_index)
|
||||
end
|
||||
|
||||
# save the output file if requested
|
||||
if @output_layout && @output_layout_file
|
||||
opt = RBA::SaveLayoutOptions::new
|
||||
gzip = opt.set_format_from_filename(@output_layout_file)
|
||||
info("Writing layout file: #{@output_layout_file} ..")
|
||||
@output_layout.write(@output_layout_file, gzip, opt)
|
||||
end
|
||||
|
||||
# create the new layers as visual layers if necessary
|
||||
if view
|
||||
|
||||
output = @output_layout || @def_layout
|
||||
cv_index = nil
|
||||
view.cellviews.times do |cvi|
|
||||
view.cellview(cvi).layout == output && cv_index = cvi
|
||||
end
|
||||
if cv_index
|
||||
_flush
|
||||
|
||||
view = RBA::LayoutView::current
|
||||
|
||||
# clear selection
|
||||
view.cancel
|
||||
|
||||
# create layer views for those layers which are not present yet
|
||||
|
||||
present_layers = {}
|
||||
l = view.begin_layers
|
||||
while !l.at_end?
|
||||
if l.current.cellview == cv_index
|
||||
present_layers[l.current.layer_index] = true
|
||||
end
|
||||
l.next
|
||||
end
|
||||
|
||||
@output_layers.each do |li|
|
||||
if !present_layers[li]
|
||||
info = @def_layout.get_info(li)
|
||||
lp = RBA::LayerProperties::new
|
||||
lp.source_layer = info.layer
|
||||
lp.source_datatype = info.datatype
|
||||
lp.source_name = info.name
|
||||
lp.source_cellview = cv_index
|
||||
view.init_layer_properties(lp)
|
||||
view.insert_layer(view.end_layers, lp)
|
||||
end
|
||||
end
|
||||
|
||||
view.update_content
|
||||
|
||||
view = RBA::LayoutView::current
|
||||
|
||||
# save the report database if requested
|
||||
if @output_rdb_file
|
||||
rdb_file = _make_path(@output_rdb_file)
|
||||
info("Writing report database: #{rdb_file} ..")
|
||||
@output_rdb.save(rdb_file)
|
||||
end
|
||||
if @output_rdb && final && view
|
||||
view.show_rdb(@output_rdb_index, view.active_cellview_index)
|
||||
end
|
||||
|
||||
# save the output file if requested
|
||||
if @output_layout && @output_layout_file
|
||||
opt = RBA::SaveLayoutOptions::new
|
||||
gzip = opt.set_format_from_filename(@output_layout_file)
|
||||
info("Writing layout file: #{@output_layout_file} ..")
|
||||
@output_layout.write(@output_layout_file, gzip, opt)
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
# save the netlist if required
|
||||
if @target_netlist_file && @netter && @netter.l2n_data
|
||||
|
||||
writer = @target_netlist_format || RBA::NetlistSpiceWriter::new
|
||||
|
||||
netlist_file = _make_path(@target_netlist_file)
|
||||
info("Writing netlist: #{netlist_file} ..")
|
||||
self.netlist.write(netlist_file, writer, @target_netlist_comment || "")
|
||||
|
||||
end
|
||||
|
||||
# save the netlist database if requested
|
||||
if @output_l2ndb_file && @netter && @netter.l2n_data
|
||||
|
||||
l2ndb_file = _make_path(@output_l2ndb_file)
|
||||
info("Writing netlist database: #{l2ndb_file} ..")
|
||||
@netter.l2n_data.write_l2n(l2ndb_file, !@output_l2ndb_long)
|
||||
|
||||
end
|
||||
|
||||
# give derived classes to perform actions
|
||||
_before_cleanup
|
||||
|
||||
# show the data in the browser
|
||||
if view && @show_l2ndb && @netter && @netter.l2n_data
|
||||
|
||||
# NOTE: to prevent the netter destroying the database, we need to take it
|
||||
l2ndb = _take_data
|
||||
l2ndb_index = view.add_l2ndb(l2ndb)
|
||||
view.show_l2ndb(l2ndb_index, view.active_cellview_index)
|
||||
|
||||
end
|
||||
|
||||
@output_layout = nil
|
||||
@output_layout_file = nil
|
||||
@output_cell = nil
|
||||
@output_rdb_file = nil
|
||||
@output_rdb_cell = nil
|
||||
@output_rdb = nil
|
||||
@output_rdb_index = nil
|
||||
@show_l2ndb = nil
|
||||
@output_l2ndb_file = nil
|
||||
|
||||
# clean up temp data
|
||||
@dss && @dss._destroy
|
||||
@dss = nil
|
||||
@netter && @netter._finish
|
||||
@netter = nil
|
||||
@netter_data = nil
|
||||
# create the new layers as visual layers if necessary
|
||||
if view
|
||||
|
||||
output = @output_layout || @def_layout
|
||||
cv_index = nil
|
||||
view.cellviews.times do |cvi|
|
||||
view.cellview(cvi).layout == output && cv_index = cvi
|
||||
end
|
||||
if cv_index
|
||||
|
||||
view = RBA::LayoutView::current
|
||||
|
||||
# clear selection
|
||||
view.cancel
|
||||
|
||||
if final && @log_file
|
||||
@log_file.close
|
||||
@log_file = nil
|
||||
# create layer views for those layers which are not present yet
|
||||
|
||||
present_layers = {}
|
||||
l = view.begin_layers
|
||||
while !l.at_end?
|
||||
if l.current.cellview == cv_index
|
||||
present_layers[l.current.layer_index] = true
|
||||
end
|
||||
l.next
|
||||
end
|
||||
|
||||
@output_layers.each do |li|
|
||||
if !present_layers[li]
|
||||
info = @def_layout.get_info(li)
|
||||
lp = RBA::LayerProperties::new
|
||||
lp.source_layer = info.layer
|
||||
lp.source_datatype = info.datatype
|
||||
lp.source_name = info.name
|
||||
lp.source_cellview = cv_index
|
||||
view.init_layer_properties(lp)
|
||||
view.insert_layer(view.end_layers, lp)
|
||||
end
|
||||
end
|
||||
|
||||
view.update_content
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
# save the netlist if required
|
||||
if @target_netlist_file && @netter && @netter.l2n_data
|
||||
|
||||
writer = @target_netlist_format || RBA::NetlistSpiceWriter::new
|
||||
|
||||
netlist_file = _make_path(@target_netlist_file)
|
||||
info("Writing netlist: #{netlist_file} ..")
|
||||
self.netlist.write(netlist_file, writer, @target_netlist_comment || "")
|
||||
|
||||
end
|
||||
|
||||
# save the netlist database if requested
|
||||
if @output_l2ndb_file && @netter && @netter.l2n_data
|
||||
|
||||
l2ndb_file = _make_path(@output_l2ndb_file)
|
||||
info("Writing netlist database: #{l2ndb_file} ..")
|
||||
@netter.l2n_data.write_l2n(l2ndb_file, !@output_l2ndb_long)
|
||||
|
||||
end
|
||||
|
||||
# give derived classes to perform actions
|
||||
_before_cleanup
|
||||
|
||||
# show the data in the browser
|
||||
if view && @show_l2ndb && @netter && @netter.l2n_data
|
||||
|
||||
# NOTE: to prevent the netter destroying the database, we need to take it
|
||||
l2ndb = _take_data
|
||||
l2ndb_index = view.add_l2ndb(l2ndb)
|
||||
view.show_l2ndb(l2ndb_index, view.active_cellview_index)
|
||||
|
||||
end
|
||||
|
||||
ensure
|
||||
|
||||
@output_layout = nil
|
||||
@output_layout_file = nil
|
||||
@output_cell = nil
|
||||
@output_rdb_file = nil
|
||||
@output_rdb_cell = nil
|
||||
@output_rdb = nil
|
||||
@output_rdb_index = nil
|
||||
@show_l2ndb = nil
|
||||
@output_l2ndb_file = nil
|
||||
|
||||
# clean up temp data
|
||||
@dss && @dss._destroy
|
||||
@dss = nil
|
||||
@netter && @netter._finish
|
||||
@netter = nil
|
||||
@netter_data = nil
|
||||
|
||||
if final && @log_file
|
||||
@log_file.close
|
||||
@log_file = nil
|
||||
end
|
||||
|
||||
# force garbage collection
|
||||
GC.start
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
|
@ -1498,7 +1509,11 @@ CODE
|
|||
# resolves the file path relative to the source's path
|
||||
sp = self.source.path
|
||||
if sp
|
||||
return File::absolute_path(file, File::dirname(sp))
|
||||
if File.respond_to?(:absolute_path)
|
||||
return File::absolute_path(file, File::dirname(sp))
|
||||
else
|
||||
return (Pathname::new(File::dirname(sp)) + Pathname.new(file)).to_s
|
||||
end
|
||||
else
|
||||
return file
|
||||
end
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ module DRC
|
|||
|
||||
ensure
|
||||
|
||||
# cleans up and creates layout views
|
||||
# cleans up and creates layout and report views
|
||||
_drc._finish
|
||||
|
||||
end
|
||||
|
|
|
|||
|
|
@ -834,6 +834,14 @@ static gsi::Class<A> decl_a ("", "A",
|
|||
#endif
|
||||
gsi::method ("*a10_prot", &A::a10_d) +
|
||||
gsi::method ("a10_f", &A::a10_f) +
|
||||
gsi::method ("a10_s", &A::a10_s) +
|
||||
gsi::method ("a10_us", &A::a10_us) +
|
||||
gsi::method ("a10_i", &A::a10_i) +
|
||||
gsi::method ("a10_l", &A::a10_l) +
|
||||
gsi::method ("a10_ll", &A::a10_ll) +
|
||||
gsi::method ("a10_ui", &A::a10_ui) +
|
||||
gsi::method ("a10_ul", &A::a10_ul) +
|
||||
gsi::method ("a10_ull", &A::a10_ull) +
|
||||
gsi::method ("a10_fptr", &A::a10_fptr) +
|
||||
gsi::method ("a10_dptr", &A::a10_dptr) +
|
||||
gsi::method ("a10_iptr", &A::a10_iptr) +
|
||||
|
|
@ -874,6 +882,14 @@ static gsi::Class<A> decl_a ("", "A",
|
|||
gsi::method ("a10_cllref", &A::a10_cllref) +
|
||||
gsi::method ("a10_cullref", &A::a10_cullref) +
|
||||
gsi::method ("a10_csref", &A::a10_csref) +
|
||||
gsi::method ("a11_s", &A::a11_s) +
|
||||
gsi::method ("a11_us", &A::a11_us) +
|
||||
gsi::method ("a11_i", &A::a11_i) +
|
||||
gsi::method ("a11_l", &A::a11_l) +
|
||||
gsi::method ("a11_ll", &A::a11_ll) +
|
||||
gsi::method ("a11_ui", &A::a11_ui) +
|
||||
gsi::method ("a11_ul", &A::a11_ul) +
|
||||
gsi::method ("a11_ull", &A::a11_ull) +
|
||||
gsi::method ("a_vp1", &A::a_vp1) +
|
||||
gsi::method ("a_vp2", &A::a_vp2) +
|
||||
gsi::method ("a9a", &A::a9a) +
|
||||
|
|
|
|||
|
|
@ -155,6 +155,15 @@ struct A
|
|||
bool a9a (int i) const { return i == 5; }
|
||||
int a9b (bool f) const { return f ? 5 : -5; }
|
||||
|
||||
short a11_s (double f) { return short(f); }
|
||||
unsigned short a11_us (double f) { return (unsigned short)(f); }
|
||||
int a11_i (double f) { return int(f); }
|
||||
unsigned int a11_ui (double f) { return (unsigned int)(f); }
|
||||
long a11_l (double f) { return long(f); }
|
||||
unsigned long a11_ul (double f) { return (unsigned long)(f); }
|
||||
long long a11_ll (double f) { return (long long)(f); }
|
||||
unsigned long long a11_ull (double f) { return (unsigned long long)(f); }
|
||||
|
||||
std::string a10_d (double f) { return tl::to_string (f); }
|
||||
#if defined(HAVE_QT)
|
||||
QByteArray a10_d_qba (double f) { return tl::to_qstring (tl::to_string (f)).toUtf8 (); }
|
||||
|
|
@ -162,6 +171,14 @@ struct A
|
|||
QStringRef a10_d_qstrref (double f) { m_s = tl::to_qstring (tl::to_string (f)); return QStringRef (&m_s); }
|
||||
#endif
|
||||
std::string a10_f (float f) { return tl::to_string(f); }
|
||||
std::string a10_s (short l) { return tl::to_string(int (l)); }
|
||||
std::string a10_us (unsigned short l) { return tl::to_string(int (l)); }
|
||||
std::string a10_i (int l) { return tl::to_string(l); }
|
||||
std::string a10_ui (unsigned int l) { return tl::to_string(l); }
|
||||
std::string a10_l (long l) { return tl::to_string(l); }
|
||||
std::string a10_ul (unsigned long l) { return tl::to_string(l); }
|
||||
std::string a10_ll (long long l) { return tl::to_string(l); }
|
||||
std::string a10_ull (unsigned long long l) { return tl::to_string(l); }
|
||||
std::string a10_fptr (float *f) { if (f) { *f += 5; return tl::to_string(*f); } else { return "nil"; } }
|
||||
std::string a10_dptr (double *f) { if (f) { *f += 6; return tl::to_string(*f); } else { return "nil"; } }
|
||||
std::string a10_iptr (int *f) { if (f) { *f += 7; return tl::to_string(*f); } else { return "nil"; } }
|
||||
|
|
|
|||
|
|
@ -235,14 +235,19 @@ NetlistBrowserPage::set_highlight_style (QColor color, int line_width, int verte
|
|||
}
|
||||
|
||||
void
|
||||
NetlistBrowserPage::set_view (lay::LayoutView *view, unsigned int cv_index)
|
||||
NetlistBrowserPage::set_view (lay::LayoutView *view, int cv_index)
|
||||
{
|
||||
if (mp_view) {
|
||||
mp_view->layer_list_changed_event.remove (this, &NetlistBrowserPage::layer_list_changed);
|
||||
}
|
||||
|
||||
mp_view = view;
|
||||
m_cv_index = cv_index;
|
||||
if (cv_index < 0) {
|
||||
mp_view = 0;
|
||||
m_cv_index = 0;
|
||||
} else {
|
||||
mp_view = view;
|
||||
m_cv_index = (unsigned int) cv_index;
|
||||
}
|
||||
|
||||
if (mp_view) {
|
||||
mp_view->layer_list_changed_event.add (this, &NetlistBrowserPage::layer_list_changed);
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ public:
|
|||
* If that pointer is non-null, the browser will attach itself to
|
||||
* the view and provide highlights for the selected markers inside the given cellview.
|
||||
*/
|
||||
void set_view (lay::LayoutView *view, unsigned int cv_index);
|
||||
void set_view (lay::LayoutView *view, int cv_index);
|
||||
|
||||
/**
|
||||
* @brief Attaches the page to a L2N DB
|
||||
|
|
|
|||
|
|
@ -131,6 +131,18 @@ module LVS
|
|||
# @synopsis max_res(threshold)
|
||||
# See \Netter#max_res for a description of that function.
|
||||
|
||||
# %LVS%
|
||||
# @name max_branch_complexity
|
||||
# @brief Configures the maximum branch complexity for ambiguous net matching
|
||||
# @synopsis max_branch_complexity(n)
|
||||
# See \Netter#max_branch_complexity for a description of that function.
|
||||
|
||||
# %LVS%
|
||||
# @name max_depth
|
||||
# @brief Configures the maximum search depth for net match deduction
|
||||
# @synopsis max_depth(n)
|
||||
# See \Netter#max_depth for a description of that function.
|
||||
|
||||
%w(schematic compare same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity).each do |f|
|
||||
eval <<"CODE"
|
||||
def #{f}(*args)
|
||||
|
|
|
|||
|
|
@ -371,11 +371,41 @@ module LVS
|
|||
@comparer.max_resistance = value.to_f
|
||||
end
|
||||
|
||||
# %LVS%
|
||||
# @name max_depth
|
||||
# @brief Configures the maximum search depth for net match deduction
|
||||
# @synopsis max_depth(n)
|
||||
# The netlist compare algorithm works recursively: once a net
|
||||
# equivalence is established, additional matches are derived from
|
||||
# this equivalence. Such equivalences in turn are used to derive
|
||||
# new equivalences and so on. The maximum depth parameter configures
|
||||
# the number of recursions the algorithm performs before picking
|
||||
# the next net. With higher values for the depth, the algorithm
|
||||
# pursues this "deduction path" in greater depth while with
|
||||
# smaller values, the algorithm prefers picking nets in a random fashion
|
||||
# as the seeds for this deduction path. The default value is 8.
|
||||
|
||||
def max_depth(value)
|
||||
lvs_data
|
||||
@comparer.max_depth = value.to_i
|
||||
end
|
||||
|
||||
# @name max_branch_complexity
|
||||
# @brief Configures the maximum branch complexity for ambiguous net matching
|
||||
# @synopsis max_branch_complexity(n)
|
||||
# The netlist compare algorithm is basically a backtracing algorithm.
|
||||
# With ambiguous nets, the algorithm picks possible net pairs and
|
||||
# tries whether they will make a good match. Following the deduction
|
||||
# path for this nets may lead to further branches if more ambiguous
|
||||
# nets are encountered. To avoid combinational explosion, the maximum
|
||||
# branch complexity is limited to the value configured with this
|
||||
# function. The default value is 100 which means not more than
|
||||
# 100 combinations are tried for a single seed pair. For networks
|
||||
# with inherent ambiguity such as decoders, the complexity
|
||||
# can be increased at the expense of potentially larger runtimes.
|
||||
# The runtime penality is roughly proportional to the branch
|
||||
# complexity.
|
||||
|
||||
def max_branch_complexity(value)
|
||||
lvs_data
|
||||
@comparer.max_branch_complexity = value.to_i
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ module LVS
|
|||
|
||||
ensure
|
||||
|
||||
# cleans up and creates layout views
|
||||
# cleans up and creates layout and report views
|
||||
_lvs._finish
|
||||
|
||||
end
|
||||
|
|
|
|||
|
|
@ -25,10 +25,12 @@
|
|||
#include "dbTestSupport.h"
|
||||
#include "dbNetlist.h"
|
||||
#include "dbNetlistSpiceReader.h"
|
||||
#include "dbNetlistCompare.h"
|
||||
#include "dbNetlistCrossReference.h"
|
||||
#include "lymMacro.h"
|
||||
#include "tlFileUtils.h"
|
||||
|
||||
void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout, bool with_l2n = false, bool with_lvsdb = false)
|
||||
void run_test (tl::TestBase *_this, const std::string &suffix, const std::string &layout)
|
||||
{
|
||||
std::string rs = tl::testsrc ();
|
||||
rs += "/testdata/lvs/" + suffix + ".lvs";
|
||||
|
|
@ -67,13 +69,33 @@ void run_test (tl::TestBase *_this, const std::string &suffix, const std::string
|
|||
lvs.load_from (rs);
|
||||
EXPECT_EQ (lvs.run (), 0);
|
||||
|
||||
_this->compare_text_files (output_cir, au_cir);
|
||||
if (with_lvsdb) {
|
||||
_this->compare_text_files (output_lvsdb, au_lvsdb);
|
||||
db::Netlist nl1, nl2;
|
||||
|
||||
{
|
||||
db::NetlistSpiceReader reader;
|
||||
tl::InputStream stream (output_cir);
|
||||
reader.read (stream, nl1);
|
||||
}
|
||||
if (with_l2n) {
|
||||
_this->compare_text_files (output_l2n, au_l2n);
|
||||
|
||||
{
|
||||
db::NetlistSpiceReader reader;
|
||||
tl::InputStream stream (au_cir);
|
||||
reader.read (stream, nl2);
|
||||
}
|
||||
|
||||
// NOTE: it's kind of redundant to use the comparer for checking the LVS
|
||||
// output, but this will essentially verify the output netlist's consistency.
|
||||
db::NetlistCrossReference xref;
|
||||
db::NetlistComparer comparer (&xref);
|
||||
comparer.set_max_branch_complexity (500);
|
||||
comparer.set_max_depth (20);
|
||||
bool res = comparer.compare (&nl1, &nl2);
|
||||
if (! res) {
|
||||
tl::info << "Netlist mismatch:";
|
||||
tl::info << " current: " << output_cir;
|
||||
tl::info << " golden: " << au_cir;
|
||||
}
|
||||
EXPECT_EQ (res, true);
|
||||
}
|
||||
|
||||
TEST(1_full)
|
||||
|
|
|
|||
|
|
@ -320,7 +320,7 @@ template <> struct python2c_func<unsigned char> : public python2c_func_cast<unsi
|
|||
template <> struct python2c_func<short> : public python2c_func_cast<short, long> { };
|
||||
template <> struct python2c_func<unsigned short> : public python2c_func_cast<unsigned short, long> { };
|
||||
template <> struct python2c_func<int> : public python2c_func_cast<int, long> { };
|
||||
template <> struct python2c_func<unsigned int> : public python2c_func_cast<unsigned int, long> { };
|
||||
template <> struct python2c_func<unsigned int> : public python2c_func_cast<unsigned int, unsigned long> { };
|
||||
|
||||
template <> PYA_PUBLIC long long python2c_func<long long>::operator() (PyObject *rval);
|
||||
template <> PYA_PUBLIC unsigned long long python2c_func<unsigned long long>::operator() (PyObject *rval);
|
||||
|
|
@ -540,7 +540,7 @@ struct c2python_func<unsigned int>
|
|||
{
|
||||
PyObject *operator() (unsigned int c)
|
||||
{
|
||||
return PyLong_FromLong (long (c));
|
||||
return PyLong_FromUnsignedLong ((unsigned long) (c));
|
||||
}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
static void run_pythontest (tl::TestBase *_this, const std::string &fn);
|
||||
|
||||
TEST (1)
|
||||
TEST (basic)
|
||||
{
|
||||
EXPECT_EQ (gsi::has_class ("Value"), true);
|
||||
EXPECT_EQ (gsi::has_class ("DoesNotExist"), false);
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
// windows.h is included before ruby.h ...
|
||||
#include "tlUnitTest.h"
|
||||
|
||||
TEST (1)
|
||||
TEST (basic)
|
||||
{
|
||||
EXPECT_EQ (gsi::has_class ("Value"), true);
|
||||
EXPECT_EQ (gsi::has_class ("DoesNotExist"), false);
|
||||
|
|
|
|||
|
|
@ -344,13 +344,49 @@ static std::string read_file (const std::string &path)
|
|||
|
||||
void TestBase::compare_text_files (const std::string &path_a, const std::string &path_b)
|
||||
{
|
||||
std::string text_a = read_file (path_a);
|
||||
std::string text_b = read_file (path_b);
|
||||
bool equal = false;
|
||||
bool any = false;
|
||||
|
||||
if (text_a != text_b) {
|
||||
raise (tl::sprintf ("Compare failed - see:\n file 1: %s\n file 2: %s",
|
||||
tl::absolute_file_path (path_a),
|
||||
tl::absolute_file_path (path_b)));
|
||||
int n = 0;
|
||||
for ( ; ! equal; ++n) {
|
||||
|
||||
std::string fn_a = path_a; // no variants for a
|
||||
std::string fn_b = path_b;
|
||||
if (n > 0) {
|
||||
fn_b += tl::sprintf (".%d", n);
|
||||
}
|
||||
|
||||
if (tl::file_exists (fn_b)) {
|
||||
|
||||
if (n == 1 && any) {
|
||||
throw tl::Exception (tl::sprintf ("Inconsistent reference variants for %s: there can be either variants (.1,.2,... suffix) or a single file (without suffix)", path_b));
|
||||
}
|
||||
|
||||
any = true;
|
||||
|
||||
std::string text_a = read_file (fn_a);
|
||||
std::string text_b = read_file (fn_b);
|
||||
|
||||
equal = (text_a == text_b);
|
||||
|
||||
if (equal && n > 0) {
|
||||
tl::info << tl::sprintf ("Found match on golden reference variant %s", fn_b);
|
||||
}
|
||||
|
||||
} else if (n > 0) {
|
||||
if (! any) {
|
||||
tl::warn << tl::sprintf ("No golden data found (%s)", path_b);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (! equal) {
|
||||
throw tl::Exception (tl::sprintf ("Compare failed - see\n actual: %s\n golden: %s%s",
|
||||
tl::absolute_file_path (path_a),
|
||||
tl::absolute_file_path (path_b),
|
||||
(n > 1 ? "\nand variants" : "")));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
#if defined(HAVE_QT)
|
||||
|
||||
# include "layApplication.h"
|
||||
# include "layMainWindow.h"
|
||||
# include "laySystemPaths.h"
|
||||
# include "layVersion.h"
|
||||
|
||||
|
|
@ -87,6 +88,13 @@ main (int argc, char **argv)
|
|||
static bool
|
||||
run_test (tl::TestBase *t, bool editable, bool slow, int repeat)
|
||||
{
|
||||
#if defined(HAVE_QT)
|
||||
// provide a clean main window without any views attached
|
||||
if (lay::MainWindow::instance ()) {
|
||||
lay::MainWindow::instance ()->close_all ();
|
||||
}
|
||||
#endif
|
||||
|
||||
for (int i = 0; i < repeat; ++i) {
|
||||
if (repeat > 1) {
|
||||
ut::noctrl << "Repeat iteration " << i + 1 << " of " << repeat;
|
||||
|
|
|
|||
|
|
@ -112,6 +112,9 @@ layout(
|
|||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1700 -2440) (3100 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(nwell (-1400 1800) (2800 3580))
|
||||
|
|
@ -259,6 +262,9 @@ layout(
|
|||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 -1640) (5740 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(BULK))
|
||||
net(2
|
||||
|
|
@ -374,6 +380,9 @@ layout(
|
|||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1720 -2440) (26880 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(FB)
|
||||
rect(diff_cont (20210 90) (220 220))
|
||||
|
|
@ -790,16 +799,17 @@ reference(
|
|||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1) param(L 0.25)
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -811,7 +821,8 @@ reference(
|
|||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3) param(L 0.25)
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -836,13 +847,13 @@ reference(
|
|||
net(7 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
pin(7 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($1)
|
||||
|
|
@ -876,10 +887,10 @@ reference(
|
|||
net(8 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
|
|
|
|||
|
|
@ -112,6 +112,9 @@ layout(
|
|||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1700 -2440) (3100 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(nwell (-1400 1800) (2800 3580))
|
||||
|
|
@ -259,6 +262,9 @@ layout(
|
|||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 -1640) (5740 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(BULK))
|
||||
net(2
|
||||
|
|
@ -374,6 +380,9 @@ layout(
|
|||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1720 -2440) (26880 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(FB)
|
||||
rect(diff_cont (20210 90) (220 220))
|
||||
|
|
@ -790,16 +799,17 @@ reference(
|
|||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1) param(L 0.25)
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -811,7 +821,8 @@ reference(
|
|||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3) param(L 0.25)
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -836,13 +847,13 @@ reference(
|
|||
net(7 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
pin(7 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($1)
|
||||
|
|
@ -876,10 +887,10 @@ reference(
|
|||
net(8 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
|
|
|
|||
|
|
@ -112,6 +112,9 @@ layout(
|
|||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1700 -2440) (3100 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(nwell (-1400 1800) (2800 3580))
|
||||
|
|
@ -259,6 +262,9 @@ layout(
|
|||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 -1640) (5740 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(BULK))
|
||||
net(2
|
||||
|
|
@ -374,6 +380,9 @@ layout(
|
|||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1720 -2440) (26880 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(FB)
|
||||
rect(diff_cont (20210 90) (220 220))
|
||||
|
|
@ -790,16 +799,17 @@ reference(
|
|||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1) param(L 0.25)
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -811,7 +821,8 @@ reference(
|
|||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3) param(L 0.25)
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -835,13 +846,13 @@ reference(
|
|||
net(6 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin()
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(name('5'))
|
||||
pin(5 name('6'))
|
||||
pin(6 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
|
|
@ -867,10 +878,10 @@ reference(
|
|||
net(8 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
|
|
@ -928,13 +939,13 @@ reference(
|
|||
net(6 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin()
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(name('5'))
|
||||
pin(5 name('6'))
|
||||
pin(6 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
|
|
|
|||
|
|
@ -112,6 +112,9 @@ layout(
|
|||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1700 -2440) (3100 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(nwell (-1400 1800) (2800 3580))
|
||||
|
|
@ -259,6 +262,9 @@ layout(
|
|||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 -1640) (5740 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(BULK))
|
||||
net(2
|
||||
|
|
@ -374,6 +380,9 @@ layout(
|
|||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1720 -2440) (26880 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(FB)
|
||||
rect(diff_cont (20210 90) (220 220))
|
||||
|
|
@ -790,16 +799,17 @@ reference(
|
|||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1) param(L 0.25)
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -811,7 +821,8 @@ reference(
|
|||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3) param(L 0.25)
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
|
|
@ -835,13 +846,13 @@ reference(
|
|||
net(6 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin()
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(name('5'))
|
||||
pin(5 name('6'))
|
||||
pin(6 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
|
|
@ -867,10 +878,10 @@ reference(
|
|||
net(8 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
|
|
@ -928,13 +939,13 @@ reference(
|
|||
net(6 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin()
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(name('5'))
|
||||
pin(5 name('6'))
|
||||
pin(6 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,971 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-1175 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,990 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (28300 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (5210 3010) (180 180))
|
||||
rect(l11 (-1350 -240) (1160 300))
|
||||
rect(l1 (-1725 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (7010 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8810 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10610 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (12410 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (14210 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (16010 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17810 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19610 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (21410 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (25210 3010) (180 180))
|
||||
rect(l8 (-22200 720) (180 180))
|
||||
rect(l11 (18880 -1140) (2900 300))
|
||||
rect(l11 (-21980 590) (320 320))
|
||||
rect(l11 (18570 -320) (320 320))
|
||||
rect(l12 (-19150 -260) (200 200))
|
||||
rect(l12 (18690 -200) (200 200))
|
||||
rect(l13 (-18840 -300) (18890 400))
|
||||
rect(l13 (-19071 -201) (2 2))
|
||||
rect(l13 (-171 -201) (400 400))
|
||||
rect(l13 (18490 -400) (400 400))
|
||||
rect(l1 (-545 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (22600 4500) (1400 3500))
|
||||
rect(l3 (-23500 -3500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (25800 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-5090 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-22280 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (25720 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-4891 1009) (2 2))
|
||||
rect(l11 (2798 -52) (2 2))
|
||||
rect(l11 (-22152 -102) (2 2))
|
||||
rect(l11 (19749 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-22751 -401) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (25900 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23300 -2550) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (-18850 -1500) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (21775 -1500) (425 1500))
|
||||
rect(l9 (-2375 -450) (500 1500))
|
||||
rect(l9 (-22600 -1500) (500 1500))
|
||||
rect(l9 (25400 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (25990 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-151 -101) (2 2))
|
||||
rect(l13 (-151 -201) (400 400))
|
||||
rect(l1 (-675 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-200 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-151 -101) (2 2))
|
||||
rect(l13 (-151 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (27010 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-3980 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-22280 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (24709 -291) (2 2))
|
||||
rect(l11 (-3852 -2) (2 2))
|
||||
rect(l11 (-19202 -102) (2 2))
|
||||
rect(l11 (23999 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l11 (-5150 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-22301 -351) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l5 (24400 460) (425 950))
|
||||
rect(l5 (-20425 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (-19525 -950) (425 950))
|
||||
rect(l10 (24325 -2210) (500 1500))
|
||||
rect(l10 (-4300 -1500) (500 1500))
|
||||
rect(l10 (-22600 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4700 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6500 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(8300 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(10100 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11900 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13700 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15500 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(17300 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(19100 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20900 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(24700 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,891 @@
|
|||
#%lvsdb-klayout
|
||||
J(
|
||||
W(RINGO)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '5/0')
|
||||
L(l8 '8/0')
|
||||
L(l11 '9/0')
|
||||
L(l12 '10/0')
|
||||
L(l13 '11/0')
|
||||
L(l7)
|
||||
L(l1)
|
||||
L(l9)
|
||||
L(l5)
|
||||
L(l10)
|
||||
C(l3 l3 l9)
|
||||
C(l4 l4 l8)
|
||||
C(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
C(l11 l8 l11 l12)
|
||||
C(l12 l11 l12 l13)
|
||||
C(l13 l12 l13)
|
||||
C(l7 l7)
|
||||
C(l1 l8 l1)
|
||||
C(l9 l3 l8 l9)
|
||||
C(l5 l8 l5)
|
||||
C(l10 l8 l10)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l10 SUBSTRATE)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (450 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$PMOS$1 PMOS
|
||||
T(S
|
||||
R(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (425 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$PMOS$2 PMOS
|
||||
T(S
|
||||
R(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (425 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l5 (-550 -475) (425 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (450 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS$1 NMOS
|
||||
T(S
|
||||
R(l5 (-575 -475) (450 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (425 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS$2 NMOS
|
||||
T(S
|
||||
R(l5 (-550 -475) (425 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (425 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(ND2X1
|
||||
R((-100 400) (2600 7600))
|
||||
N(1 I(VDD)
|
||||
R(l8 (1110 5160) (180 180))
|
||||
R(l8 (-180 920) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l11 (-240 -790) (300 1700))
|
||||
R(l11 (-1350 0) (2400 800))
|
||||
R(l11 (-1151 -401) (2 2))
|
||||
R(l1 (-276 -2151) (425 1500))
|
||||
R(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
N(2 I(OUT)
|
||||
R(l8 (1810 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-1580 3760) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (1220 920) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
R(l11 (-110 1390) (300 1400))
|
||||
Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
R(l11 (-141 -501) (2 2))
|
||||
R(l11 (-1751 1099) (300 1400))
|
||||
R(l11 (1100 -1700) (300 300))
|
||||
R(l11 (-300 0) (300 1400))
|
||||
R(l1 (-375 -1450) (425 1500))
|
||||
R(l1 (-1800 -1500) (425 1500))
|
||||
R(l5 (950 -4890) (425 950))
|
||||
)
|
||||
N(3 I(VSS)
|
||||
R(l8 (410 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -1300) (300 1360))
|
||||
R(l11 (-650 -2160) (2400 800))
|
||||
R(l11 (-1151 -401) (2 2))
|
||||
R(l5 (-951 859) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
N(5 I(B)
|
||||
R(l4 (1425 2860) (250 1940))
|
||||
R(l4 (-345 -950) (300 300))
|
||||
R(l4 (-205 650) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-285 1050) (180 180))
|
||||
R(l11 (-71 -91) (2 2))
|
||||
R(l11 (-171 -151) (300 300))
|
||||
)
|
||||
N(6 I(A)
|
||||
R(l4 (725 2860) (250 1940))
|
||||
R(l4 (-325 -1850) (300 300))
|
||||
R(l4 (-225 1550) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-265 150) (180 180))
|
||||
R(l11 (-91 -91) (2 2))
|
||||
R(l11 (-151 -151) (300 300))
|
||||
)
|
||||
N(7 I(SUBSTRATE))
|
||||
N(8
|
||||
R(l5 (975 1660) (425 950))
|
||||
R(l5 (-400 -950) (425 950))
|
||||
)
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4)
|
||||
P(5 I(B))
|
||||
P(6 I(A))
|
||||
P(7 I(SUBSTRATE))
|
||||
D(1 D$PMOS
|
||||
Y(850 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.6375)
|
||||
E(AD 0.3375)
|
||||
E(PS 3.85)
|
||||
E(PD 1.95)
|
||||
T(S 2)
|
||||
T(G 6)
|
||||
T(D 1)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 D$PMOS$1
|
||||
Y(1550 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.3375)
|
||||
E(AD 0.6375)
|
||||
E(PS 1.95)
|
||||
E(PD 3.85)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(3 D$NMOS
|
||||
Y(850 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.40375)
|
||||
E(AD 0.21375)
|
||||
E(PS 2.75)
|
||||
E(PD 1.4)
|
||||
T(S 3)
|
||||
T(G 6)
|
||||
T(D 8)
|
||||
T(B 7)
|
||||
)
|
||||
D(4 D$NMOS$1
|
||||
Y(1550 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.21375)
|
||||
E(AD 0.40375)
|
||||
E(PS 1.4)
|
||||
E(PD 2.75)
|
||||
T(S 8)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 7)
|
||||
)
|
||||
)
|
||||
X(INVX1
|
||||
R((-100 400) (2000 7600))
|
||||
N(1 I(VDD)
|
||||
R(l8 (410 6260) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l11 (-240 -240) (300 1400))
|
||||
R(l11 (-650 300) (1800 800))
|
||||
R(l11 (-1450 -1100) (300 300))
|
||||
R(l11 (299 399) (2 2))
|
||||
R(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
N(2 I(OUT)
|
||||
R(l8 (1110 5160) (180 180))
|
||||
R(l8 (-180 920) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -4120) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -790) (300 4790))
|
||||
R(l11 (-151 -2501) (2 2))
|
||||
R(l1 (-226 1049) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(3 I(VSS)
|
||||
R(l8 (410 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -1300) (300 1360))
|
||||
R(l11 (-650 -2160) (1800 800))
|
||||
R(l11 (-851 -401) (2 2))
|
||||
R(l5 (-651 859) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
N(5 I(IN)
|
||||
R(l4 (725 2860) (250 1940))
|
||||
R(l4 (-525 -1850) (300 300))
|
||||
R(l4 (-25 1550) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-465 150) (180 180))
|
||||
R(l11 (-91 -91) (2 2))
|
||||
R(l11 (-151 -151) (300 300))
|
||||
)
|
||||
N(6 I(SUBSTRATE))
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4)
|
||||
P(5 I(IN))
|
||||
P(6 I(SUBSTRATE))
|
||||
D(1 D$PMOS$2
|
||||
Y(850 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.6375)
|
||||
E(AD 0.6375)
|
||||
E(PS 3.85)
|
||||
E(PD 3.85)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 D$NMOS$2
|
||||
Y(850 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.40375)
|
||||
E(AD 0.40375)
|
||||
E(PS 2.75)
|
||||
E(PD 2.75)
|
||||
T(S 3)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
X(RINGO
|
||||
R((0 350) (25800 7650))
|
||||
N(1
|
||||
R(l8 (4710 3010) (180 180))
|
||||
R(l11 (-850 -240) (610 300))
|
||||
R(l1 (-1175 1800) (425 1500))
|
||||
R(l1 (-1800 -1500) (425 1500))
|
||||
R(l5 (950 -4890) (425 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (6510 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(3
|
||||
R(l8 (8310 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l8 (10110 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(5
|
||||
R(l8 (11910 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(6
|
||||
R(l8 (13710 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(7
|
||||
R(l8 (15510 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(8
|
||||
R(l8 (17310 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(9
|
||||
R(l8 (19110 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(10
|
||||
R(l8 (20910 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(11 I(FB)
|
||||
R(l8 (22710 3010) (180 180))
|
||||
R(l8 (-19700 720) (180 180))
|
||||
R(l11 (18380 -1140) (900 300))
|
||||
R(l11 (-19530 590) (320 320))
|
||||
R(l11 (17820 -320) (320 320))
|
||||
R(l12 (-18400 -260) (200 200))
|
||||
R(l12 (17940 -200) (200 200))
|
||||
R(l13 (-18040 -300) (17740 400))
|
||||
R(l13 (-17921 -201) (2 2))
|
||||
R(l13 (-221 -201) (400 400))
|
||||
R(l13 (17740 -400) (400 400))
|
||||
R(l1 (-245 850) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(12 I(VDD)
|
||||
R(l3 (500 4500) (1400 3500))
|
||||
R(l3 (-1900 -3500) (600 3500))
|
||||
R(l3 (23300 -3500) (1400 3500))
|
||||
R(l3 (-100 -3500) (600 3500))
|
||||
R(l8 (-24690 -1240) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (23220 370) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l11 (-21741 859) (2 2))
|
||||
R(l11 (-2351 -451) (1200 800))
|
||||
R(l11 (-750 -1450) (300 1400))
|
||||
R(l11 (-101 -351) (2 2))
|
||||
R(l11 (-1251 -401) (600 800))
|
||||
R(l11 (23400 -800) (1200 800))
|
||||
R(l11 (-750 -1450) (300 1400))
|
||||
R(l11 (-101 -351) (2 2))
|
||||
R(l11 (549 -401) (600 800))
|
||||
R(l1 (-23025 -2550) (425 1500))
|
||||
R(l1 (-400 -1500) (425 1500))
|
||||
R(l1 (1275 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l9 (-21975 -450) (500 1500))
|
||||
R(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
N(13 I(OUT)
|
||||
R(l11 (23440 3840) (320 320))
|
||||
R(l12 (-260 -260) (200 200))
|
||||
R(l13 (-101 -101) (2 2))
|
||||
R(l13 (-201 -201) (400 400))
|
||||
R(l1 (-625 850) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(14 I(ENABLE)
|
||||
R(l8 (2510 3010) (180 180))
|
||||
R(l11 (-250 -250) (320 320))
|
||||
R(l12 (-260 -260) (200 200))
|
||||
R(l13 (-101 -101) (2 2))
|
||||
R(l13 (-201 -201) (400 400))
|
||||
)
|
||||
N(15 I(VSS)
|
||||
R(l8 (1110 1610) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (23220 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-21741 -391) (2 2))
|
||||
R(l11 (-1901 -401) (300 1400))
|
||||
R(l11 (-750 -1450) (1200 800))
|
||||
R(l11 (-551 -401) (2 2))
|
||||
R(l11 (-1251 -401) (600 800))
|
||||
R(l11 (23850 -750) (300 1400))
|
||||
R(l11 (-750 -1450) (1200 800))
|
||||
R(l11 (-551 -401) (2 2))
|
||||
R(l11 (549 -401) (600 800))
|
||||
R(l5 (-23700 460) (425 950))
|
||||
R(l5 (1975 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l10 (-21975 -2210) (500 1500))
|
||||
R(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
P(11 I(FB))
|
||||
P(12 I(VDD))
|
||||
P(13 I(OUT))
|
||||
P(14 I(ENABLE))
|
||||
P(15 I(VSS))
|
||||
X(1 ND2X1 Y(1800 0)
|
||||
P(0 12)
|
||||
P(1 1)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 11)
|
||||
P(5 14)
|
||||
P(6 15)
|
||||
)
|
||||
X(2 INVX1 Y(4200 0)
|
||||
P(0 12)
|
||||
P(1 2)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 1)
|
||||
P(5 15)
|
||||
)
|
||||
X(3 INVX1 Y(6000 0)
|
||||
P(0 12)
|
||||
P(1 3)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 2)
|
||||
P(5 15)
|
||||
)
|
||||
X(4 INVX1 Y(7800 0)
|
||||
P(0 12)
|
||||
P(1 4)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 3)
|
||||
P(5 15)
|
||||
)
|
||||
X(5 INVX1 Y(9600 0)
|
||||
P(0 12)
|
||||
P(1 5)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 4)
|
||||
P(5 15)
|
||||
)
|
||||
X(6 INVX1 Y(11400 0)
|
||||
P(0 12)
|
||||
P(1 6)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 5)
|
||||
P(5 15)
|
||||
)
|
||||
X(7 INVX1 Y(13200 0)
|
||||
P(0 12)
|
||||
P(1 7)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 6)
|
||||
P(5 15)
|
||||
)
|
||||
X(8 INVX1 Y(15000 0)
|
||||
P(0 12)
|
||||
P(1 8)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 7)
|
||||
P(5 15)
|
||||
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|
||||
X(9 INVX1 Y(16800 0)
|
||||
P(0 12)
|
||||
P(1 9)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 8)
|
||||
P(5 15)
|
||||
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|
||||
X(10 INVX1 Y(18600 0)
|
||||
P(0 12)
|
||||
P(1 10)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 9)
|
||||
P(5 15)
|
||||
)
|
||||
X(11 INVX1 Y(20400 0)
|
||||
P(0 12)
|
||||
P(1 11)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 10)
|
||||
P(5 15)
|
||||
)
|
||||
X(12 INVX1 Y(22200 0)
|
||||
P(0 12)
|
||||
P(1 13)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 11)
|
||||
P(5 15)
|
||||
)
|
||||
)
|
||||
)
|
||||
H(
|
||||
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|
||||
N(1 I(VDD))
|
||||
N(2 I(OUT))
|
||||
N(3 I(VSS))
|
||||
N(4 I(NWELL))
|
||||
N(5 I(B))
|
||||
N(6 I(A))
|
||||
N(7 I(BULK))
|
||||
N(8 I('1'))
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4 I(NWELL))
|
||||
P(5 I(B))
|
||||
P(6 I(A))
|
||||
P(7 I(BULK))
|
||||
D(1 PMOS
|
||||
I($1)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(G 6)
|
||||
T(D 1)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 PMOS
|
||||
I($2)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(3 NMOS
|
||||
I($3)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 3)
|
||||
T(G 6)
|
||||
T(D 8)
|
||||
T(B 7)
|
||||
)
|
||||
D(4 NMOS
|
||||
I($4)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 8)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 7)
|
||||
)
|
||||
)
|
||||
X(INVX1
|
||||
N(1 I(VDD))
|
||||
N(2 I(OUT))
|
||||
N(3 I(VSS))
|
||||
N(4 I(NWELL))
|
||||
N(5 I(IN))
|
||||
N(6 I(BULK))
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4 I(NWELL))
|
||||
P(5 I(IN))
|
||||
P(6 I(BULK))
|
||||
D(1 PMOS
|
||||
I($1)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 NMOS
|
||||
I($2)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 3)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
X(RINGO
|
||||
N(1 I(VSS))
|
||||
N(2 I(VDD))
|
||||
N(3 I(FB))
|
||||
N(4 I(ENABLE))
|
||||
N(5 I(OUT))
|
||||
N(6 I('1'))
|
||||
N(7 I('2'))
|
||||
N(8 I('3'))
|
||||
N(9 I('4'))
|
||||
N(10 I('5'))
|
||||
N(11 I('6'))
|
||||
N(12 I('7'))
|
||||
N(13 I('8'))
|
||||
N(14 I('9'))
|
||||
N(15 I('10'))
|
||||
P(1 I(VSS))
|
||||
P(2 I(VDD))
|
||||
P(3 I(FB))
|
||||
P(4 I(ENABLE))
|
||||
P(5 I(OUT))
|
||||
X(1 ND2X1 I($1)
|
||||
P(0 2)
|
||||
P(1 6)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 3)
|
||||
P(5 4)
|
||||
P(6 1)
|
||||
)
|
||||
X(2 INVX1 I($2)
|
||||
P(0 2)
|
||||
P(1 7)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 6)
|
||||
P(5 1)
|
||||
)
|
||||
X(3 INVX1 I($3)
|
||||
P(0 2)
|
||||
P(1 8)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 7)
|
||||
P(5 1)
|
||||
)
|
||||
X(4 INVX1 I($4)
|
||||
P(0 2)
|
||||
P(1 9)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 8)
|
||||
P(5 1)
|
||||
)
|
||||
X(5 INVX1 I($5)
|
||||
P(0 2)
|
||||
P(1 10)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 9)
|
||||
P(5 1)
|
||||
)
|
||||
X(6 INVX1 I($6)
|
||||
P(0 2)
|
||||
P(1 11)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 10)
|
||||
P(5 1)
|
||||
)
|
||||
X(7 INVX1 I($7)
|
||||
P(0 2)
|
||||
P(1 12)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 11)
|
||||
P(5 1)
|
||||
)
|
||||
X(8 INVX1 I($8)
|
||||
P(0 2)
|
||||
P(1 13)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 12)
|
||||
P(5 1)
|
||||
)
|
||||
X(9 INVX1 I($9)
|
||||
P(0 2)
|
||||
P(1 14)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 13)
|
||||
P(5 1)
|
||||
)
|
||||
X(10 INVX1 I($10)
|
||||
P(0 2)
|
||||
P(1 15)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 14)
|
||||
P(5 1)
|
||||
)
|
||||
X(11 INVX1 I($11)
|
||||
P(0 2)
|
||||
P(1 3)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 15)
|
||||
P(5 1)
|
||||
)
|
||||
X(12 INVX1 I($12)
|
||||
P(0 2)
|
||||
P(1 5)
|
||||
P(2 1)
|
||||
P(3 2)
|
||||
P(4 3)
|
||||
P(5 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
Z(
|
||||
X(INVX1 INVX1 1
|
||||
Z(
|
||||
N(4 4 1)
|
||||
N(5 5 1)
|
||||
N(2 2 1)
|
||||
N(6 6 1)
|
||||
N(1 1 1)
|
||||
N(3 3 1)
|
||||
P(3 3 1)
|
||||
P(4 4 1)
|
||||
P(1 1 1)
|
||||
P(5 5 1)
|
||||
P(0 0 1)
|
||||
P(2 2 1)
|
||||
D(1 1 1)
|
||||
D(2 2 1)
|
||||
)
|
||||
)
|
||||
X(ND2X1 ND2X1 1
|
||||
Z(
|
||||
N(8 8 1)
|
||||
N(4 4 1)
|
||||
N(6 6 1)
|
||||
N(5 5 1)
|
||||
N(2 2 1)
|
||||
N(7 7 1)
|
||||
N(1 1 1)
|
||||
N(3 3 1)
|
||||
P(3 3 1)
|
||||
P(5 5 1)
|
||||
P(4 4 1)
|
||||
P(1 1 1)
|
||||
P(6 6 1)
|
||||
P(0 0 1)
|
||||
P(2 2 1)
|
||||
D(1 1 1)
|
||||
D(2 2 1)
|
||||
D(3 3 1)
|
||||
D(4 4 1)
|
||||
)
|
||||
)
|
||||
X(RINGO RINGO 1
|
||||
Z(
|
||||
N(1 6 1)
|
||||
N(10 15 1)
|
||||
N(2 7 1)
|
||||
N(3 8 1)
|
||||
N(4 9 1)
|
||||
N(5 10 1)
|
||||
N(6 11 1)
|
||||
N(7 12 1)
|
||||
N(8 13 1)
|
||||
N(9 14 1)
|
||||
N(14 4 1)
|
||||
N(11 3 1)
|
||||
N(13 5 1)
|
||||
N(12 2 1)
|
||||
N(15 1 1)
|
||||
P(3 3 1)
|
||||
P(0 2 1)
|
||||
P(2 4 1)
|
||||
P(1 1 1)
|
||||
P(4 0 1)
|
||||
X(1 1 1)
|
||||
X(10 10 1)
|
||||
X(11 11 1)
|
||||
X(12 12 1)
|
||||
X(2 2 1)
|
||||
X(3 3 1)
|
||||
X(4 4 1)
|
||||
X(5 5 1)
|
||||
X(6 6 1)
|
||||
X(7 7 1)
|
||||
X(8 8 1)
|
||||
X(9 9 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
* Extracted by KLayout
|
||||
.INCLUDE 'models.cir'
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
X$1 VDD IN OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.6375 PS=3.85 PD=3.85
|
||||
X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.40375
|
||||
+ PS=2.75 PD=2.75
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
X$1 OUT A VDD \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.3375 PS=3.85 PD=1.95
|
||||
X$2 VDD B OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.3375 AD=0.6375 PS=1.95 PD=3.85
|
||||
X$3 VSS A \$I5 SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.21375
|
||||
+ PS=2.75 PD=1.4
|
||||
X$4 \$I5 B OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.21375 AD=0.40375
|
||||
+ PS=1.4 PD=2.75
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,580 @@
|
|||
#%l2n-klayout
|
||||
W(RINGO)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '5/0')
|
||||
L(l8 '8/0')
|
||||
L(l11 '9/0')
|
||||
L(l12 '10/0')
|
||||
L(l13 '11/0')
|
||||
L(l7)
|
||||
L(l1)
|
||||
L(l9)
|
||||
L(l5)
|
||||
L(l10)
|
||||
C(l3 l3 l9)
|
||||
C(l4 l4 l8)
|
||||
C(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
C(l11 l8 l11 l12)
|
||||
C(l12 l11 l12 l13)
|
||||
C(l13 l12 l13)
|
||||
C(l7 l7)
|
||||
C(l1 l8 l1)
|
||||
C(l9 l3 l8 l9)
|
||||
C(l5 l8 l5)
|
||||
C(l10 l8 l10)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l10 SUBSTRATE)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (450 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$PMOS$1 PMOS
|
||||
T(S
|
||||
R(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (425 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$PMOS$2 PMOS
|
||||
T(S
|
||||
R(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
T(D
|
||||
R(l1 (125 -750) (425 1500))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l5 (-550 -475) (425 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (450 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS$1 NMOS
|
||||
T(S
|
||||
R(l5 (-575 -475) (450 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (425 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS$2 NMOS
|
||||
T(S
|
||||
R(l5 (-550 -475) (425 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (425 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(ND2X1
|
||||
R((-100 400) (2600 7600))
|
||||
N(1 I(VDD)
|
||||
R(l8 (1110 5160) (180 180))
|
||||
R(l8 (-180 920) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l11 (-240 -790) (300 1700))
|
||||
R(l11 (-1350 0) (2400 800))
|
||||
R(l11 (-1151 -401) (2 2))
|
||||
R(l1 (-276 -2151) (425 1500))
|
||||
R(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
N(2 I(OUT)
|
||||
R(l8 (1810 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-1580 3760) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (1220 920) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
R(l11 (-110 1390) (300 1400))
|
||||
Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
R(l11 (-141 -501) (2 2))
|
||||
R(l11 (-1751 1099) (300 1400))
|
||||
R(l11 (1100 -1700) (300 300))
|
||||
R(l11 (-300 0) (300 1400))
|
||||
R(l1 (-375 -1450) (425 1500))
|
||||
R(l1 (-1800 -1500) (425 1500))
|
||||
R(l5 (950 -4890) (425 950))
|
||||
)
|
||||
N(3 I(VSS)
|
||||
R(l8 (410 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -1300) (300 1360))
|
||||
R(l11 (-650 -2160) (2400 800))
|
||||
R(l11 (-1151 -401) (2 2))
|
||||
R(l5 (-951 859) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
N(5 I(B)
|
||||
R(l4 (1425 2860) (250 1940))
|
||||
R(l4 (-345 -950) (300 300))
|
||||
R(l4 (-205 650) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-285 1050) (180 180))
|
||||
R(l11 (-71 -91) (2 2))
|
||||
R(l11 (-171 -151) (300 300))
|
||||
)
|
||||
N(6 I(A)
|
||||
R(l4 (725 2860) (250 1940))
|
||||
R(l4 (-325 -1850) (300 300))
|
||||
R(l4 (-225 1550) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-265 150) (180 180))
|
||||
R(l11 (-91 -91) (2 2))
|
||||
R(l11 (-151 -151) (300 300))
|
||||
)
|
||||
N(7 I(SUBSTRATE))
|
||||
N(8
|
||||
R(l5 (975 1660) (425 950))
|
||||
R(l5 (-400 -950) (425 950))
|
||||
)
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4)
|
||||
P(5 I(B))
|
||||
P(6 I(A))
|
||||
P(7 I(SUBSTRATE))
|
||||
D(1 D$PMOS
|
||||
Y(850 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.6375)
|
||||
E(AD 0.3375)
|
||||
E(PS 3.85)
|
||||
E(PD 1.95)
|
||||
T(S 2)
|
||||
T(G 6)
|
||||
T(D 1)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 D$PMOS$1
|
||||
Y(1550 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.3375)
|
||||
E(AD 0.6375)
|
||||
E(PS 1.95)
|
||||
E(PD 3.85)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(3 D$NMOS
|
||||
Y(850 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.40375)
|
||||
E(AD 0.21375)
|
||||
E(PS 2.75)
|
||||
E(PD 1.4)
|
||||
T(S 3)
|
||||
T(G 6)
|
||||
T(D 8)
|
||||
T(B 7)
|
||||
)
|
||||
D(4 D$NMOS$1
|
||||
Y(1550 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.21375)
|
||||
E(AD 0.40375)
|
||||
E(PS 1.4)
|
||||
E(PD 2.75)
|
||||
T(S 8)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 7)
|
||||
)
|
||||
)
|
||||
X(INVX1
|
||||
R((-100 400) (2000 7600))
|
||||
N(1 I(VDD)
|
||||
R(l8 (410 6260) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l11 (-240 -240) (300 1400))
|
||||
R(l11 (-650 300) (1800 800))
|
||||
R(l11 (-1450 -1100) (300 300))
|
||||
R(l11 (299 399) (2 2))
|
||||
R(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
N(2 I(OUT)
|
||||
R(l8 (1110 5160) (180 180))
|
||||
R(l8 (-180 920) (180 180))
|
||||
R(l8 (-180 -730) (180 180))
|
||||
R(l8 (-180 -4120) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -790) (300 4790))
|
||||
R(l11 (-151 -2501) (2 2))
|
||||
R(l1 (-226 1049) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(3 I(VSS)
|
||||
R(l8 (410 1770) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-240 -1300) (300 1360))
|
||||
R(l11 (-650 -2160) (1800 800))
|
||||
R(l11 (-851 -401) (2 2))
|
||||
R(l5 (-651 859) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
N(5 I(IN)
|
||||
R(l4 (725 2860) (250 1940))
|
||||
R(l4 (-525 -1850) (300 300))
|
||||
R(l4 (-25 1550) (250 2000))
|
||||
R(l4 (-250 -2000) (250 2000))
|
||||
R(l4 (-250 -5390) (250 1450))
|
||||
R(l8 (-465 150) (180 180))
|
||||
R(l11 (-91 -91) (2 2))
|
||||
R(l11 (-151 -151) (300 300))
|
||||
)
|
||||
N(6 I(SUBSTRATE))
|
||||
P(1 I(VDD))
|
||||
P(2 I(OUT))
|
||||
P(3 I(VSS))
|
||||
P(4)
|
||||
P(5 I(IN))
|
||||
P(6 I(SUBSTRATE))
|
||||
D(1 D$PMOS$2
|
||||
Y(850 5800)
|
||||
E(L 0.25)
|
||||
E(W 1.5)
|
||||
E(AS 0.6375)
|
||||
E(AD 0.6375)
|
||||
E(PS 3.85)
|
||||
E(PD 3.85)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 D$NMOS$2
|
||||
Y(850 2135)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.40375)
|
||||
E(AD 0.40375)
|
||||
E(PS 2.75)
|
||||
E(PD 2.75)
|
||||
T(S 3)
|
||||
T(G 5)
|
||||
T(D 2)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
X(RINGO
|
||||
R((0 350) (25800 7650))
|
||||
N(1
|
||||
R(l8 (4710 3010) (180 180))
|
||||
R(l11 (-850 -240) (610 300))
|
||||
R(l1 (-1175 1800) (425 1500))
|
||||
R(l1 (-1800 -1500) (425 1500))
|
||||
R(l5 (950 -4890) (425 950))
|
||||
)
|
||||
N(2
|
||||
R(l8 (6510 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(3
|
||||
R(l8 (8310 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(4
|
||||
R(l8 (10110 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(5
|
||||
R(l8 (11910 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(6
|
||||
R(l8 (13710 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(7
|
||||
R(l8 (15510 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(8
|
||||
R(l8 (17310 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(9
|
||||
R(l8 (19110 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(10
|
||||
R(l8 (20910 3010) (180 180))
|
||||
R(l11 (-1140 -240) (900 300))
|
||||
R(l1 (-1275 1800) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(11 I(FB)
|
||||
R(l8 (22710 3010) (180 180))
|
||||
R(l8 (-19700 720) (180 180))
|
||||
R(l11 (18380 -1140) (900 300))
|
||||
R(l11 (-19530 590) (320 320))
|
||||
R(l11 (17820 -320) (320 320))
|
||||
R(l12 (-18400 -260) (200 200))
|
||||
R(l12 (17940 -200) (200 200))
|
||||
R(l13 (-18040 -300) (17740 400))
|
||||
R(l13 (-17921 -201) (2 2))
|
||||
R(l13 (-221 -201) (400 400))
|
||||
R(l13 (17740 -400) (400 400))
|
||||
R(l1 (-245 850) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(12 I(VDD)
|
||||
R(l3 (500 4500) (1400 3500))
|
||||
R(l3 (-1900 -3500) (600 3500))
|
||||
R(l3 (23300 -3500) (1400 3500))
|
||||
R(l3 (-100 -3500) (600 3500))
|
||||
R(l8 (-24690 -1240) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (23220 370) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l11 (-21741 859) (2 2))
|
||||
R(l11 (-2351 -451) (1200 800))
|
||||
R(l11 (-750 -1450) (300 1400))
|
||||
R(l11 (-101 -351) (2 2))
|
||||
R(l11 (-1251 -401) (600 800))
|
||||
R(l11 (23400 -800) (1200 800))
|
||||
R(l11 (-750 -1450) (300 1400))
|
||||
R(l11 (-101 -351) (2 2))
|
||||
R(l11 (549 -401) (600 800))
|
||||
R(l1 (-23025 -2550) (425 1500))
|
||||
R(l1 (-400 -1500) (425 1500))
|
||||
R(l1 (1275 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l1 (1375 -1500) (425 1500))
|
||||
R(l9 (-21975 -450) (500 1500))
|
||||
R(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
N(13 I(OUT)
|
||||
R(l11 (23440 3840) (320 320))
|
||||
R(l12 (-260 -260) (200 200))
|
||||
R(l13 (-101 -101) (2 2))
|
||||
R(l13 (-201 -201) (400 400))
|
||||
R(l1 (-625 850) (425 1500))
|
||||
R(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
N(14 I(ENABLE)
|
||||
R(l8 (2510 3010) (180 180))
|
||||
R(l11 (-250 -250) (320 320))
|
||||
R(l12 (-260 -260) (200 200))
|
||||
R(l13 (-101 -101) (2 2))
|
||||
R(l13 (-201 -201) (400 400))
|
||||
)
|
||||
N(15 I(VSS)
|
||||
R(l8 (1110 1610) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l8 (23220 370) (180 180))
|
||||
R(l8 (-180 -1280) (180 180))
|
||||
R(l8 (-180 370) (180 180))
|
||||
R(l11 (-21741 -391) (2 2))
|
||||
R(l11 (-1901 -401) (300 1400))
|
||||
R(l11 (-750 -1450) (1200 800))
|
||||
R(l11 (-551 -401) (2 2))
|
||||
R(l11 (-1251 -401) (600 800))
|
||||
R(l11 (23850 -750) (300 1400))
|
||||
R(l11 (-750 -1450) (1200 800))
|
||||
R(l11 (-551 -401) (2 2))
|
||||
R(l11 (549 -401) (600 800))
|
||||
R(l5 (-23700 460) (425 950))
|
||||
R(l5 (1975 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l5 (1375 -950) (425 950))
|
||||
R(l10 (-21975 -2210) (500 1500))
|
||||
R(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
P(11 I(FB))
|
||||
P(12 I(VDD))
|
||||
P(13 I(OUT))
|
||||
P(14 I(ENABLE))
|
||||
P(15 I(VSS))
|
||||
X(1 ND2X1 Y(1800 0)
|
||||
P(0 12)
|
||||
P(1 1)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 11)
|
||||
P(5 14)
|
||||
P(6 15)
|
||||
)
|
||||
X(2 INVX1 Y(4200 0)
|
||||
P(0 12)
|
||||
P(1 2)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 1)
|
||||
P(5 15)
|
||||
)
|
||||
X(3 INVX1 Y(6000 0)
|
||||
P(0 12)
|
||||
P(1 3)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 2)
|
||||
P(5 15)
|
||||
)
|
||||
X(4 INVX1 Y(7800 0)
|
||||
P(0 12)
|
||||
P(1 4)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 3)
|
||||
P(5 15)
|
||||
)
|
||||
X(5 INVX1 Y(9600 0)
|
||||
P(0 12)
|
||||
P(1 5)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 4)
|
||||
P(5 15)
|
||||
)
|
||||
X(6 INVX1 Y(11400 0)
|
||||
P(0 12)
|
||||
P(1 6)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 5)
|
||||
P(5 15)
|
||||
)
|
||||
X(7 INVX1 Y(13200 0)
|
||||
P(0 12)
|
||||
P(1 7)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 6)
|
||||
P(5 15)
|
||||
)
|
||||
X(8 INVX1 Y(15000 0)
|
||||
P(0 12)
|
||||
P(1 8)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 7)
|
||||
P(5 15)
|
||||
)
|
||||
X(9 INVX1 Y(16800 0)
|
||||
P(0 12)
|
||||
P(1 9)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 8)
|
||||
P(5 15)
|
||||
)
|
||||
X(10 INVX1 Y(18600 0)
|
||||
P(0 12)
|
||||
P(1 10)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 9)
|
||||
P(5 15)
|
||||
)
|
||||
X(11 INVX1 Y(20400 0)
|
||||
P(0 12)
|
||||
P(1 11)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 10)
|
||||
P(5 15)
|
||||
)
|
||||
X(12 INVX1 Y(22200 0)
|
||||
P(0 12)
|
||||
P(1 13)
|
||||
P(2 15)
|
||||
P(3 12)
|
||||
P(4 11)
|
||||
P(5 15)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,971 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-1175 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,970 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(top)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(nd2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INV
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(top
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-1175 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 nd2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INV location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INV location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INV location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INV location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INV location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INV location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INV location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INV location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INV location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INV location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INV location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INV INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(nd2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(top RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,971 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-1175 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(A))
|
||||
net(6 name(B))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(A))
|
||||
pin(6 name(B))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 6)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 6)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 5 match)
|
||||
net(5 6 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 4 match)
|
||||
pin(4 5 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I5 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,971 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l1)
|
||||
layer(l9)
|
||||
layer(l5)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l1 l9 l5 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l1 l8 l1)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l5 l8 l5)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PM MOS4)
|
||||
class(NM MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PM PM
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PM$1 PM
|
||||
terminal(S
|
||||
rect(l1 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PM$2 PM
|
||||
terminal(S
|
||||
rect(l1 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l1 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NM NM
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NM$1 NM
|
||||
terminal(S
|
||||
rect(l5 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NM$2 NM
|
||||
terminal(S
|
||||
rect(l5 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l5 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l1 (-276 -2151) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l1 (-375 -1450) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l5 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l5 (975 1660) (425 950))
|
||||
rect(l5 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PM
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PM$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NM
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NM$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l1 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l1 (-226 1049) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l5 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PM$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NM$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l8 (4710 3010) (180 180))
|
||||
rect(l11 (-850 -240) (610 300))
|
||||
rect(l1 (-1175 1800) (425 1500))
|
||||
rect(l1 (-1800 -1500) (425 1500))
|
||||
rect(l5 (950 -4890) (425 950))
|
||||
)
|
||||
net(2
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l1 (-1275 1800) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l8 (22710 3010) (180 180))
|
||||
rect(l8 (-19700 720) (180 180))
|
||||
rect(l11 (18380 -1140) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
rect(l1 (-245 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l1 (-23025 -2550) (425 1500))
|
||||
rect(l1 (-400 -1500) (425 1500))
|
||||
rect(l1 (1275 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l1 (1375 -1500) (425 1500))
|
||||
rect(l9 (-21975 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l1 (-625 850) (425 1500))
|
||||
rect(l5 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l8 (2510 3010) (180 180))
|
||||
rect(l11 (-250 -250) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l5 (-23700 460) (425 950))
|
||||
rect(l5 (1975 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l5 (1375 -950) (425 950))
|
||||
rect(l10 (-21975 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -412,6 +412,26 @@ class BasicTest(unittest.TestCase):
|
|||
self.assertEqual( a3.a1(), -11 )
|
||||
|
||||
self.assertEqual( a1.a10_d(5.2), "5.2" )
|
||||
self.assertEqual( a1.a10_s(0x70000000), "0" )
|
||||
self.assertEqual( a1.a10_s(0x7fffffff), "-1" )
|
||||
self.assertEqual( a1.a10_us(0x70000000), "0" )
|
||||
self.assertEqual( a1.a10_us(0x7fffffff), "65535" )
|
||||
self.assertEqual( a1.a10_i(-0x80000000), "-2147483648" )
|
||||
self.assertEqual( a1.a10_l(-0x80000000), "-2147483648" )
|
||||
self.assertEqual( a1.a10_ll(-0x80000000), "-2147483648" )
|
||||
self.assertEqual( a1.a10_ui(0xffffffff), "4294967295" )
|
||||
self.assertEqual( a1.a10_ul(0xffffffff), "4294967295" )
|
||||
self.assertEqual( a1.a10_ull(0xffffffff), "4294967295" )
|
||||
self.assertEqual( a1.a11_s(0x70000000), 0 )
|
||||
self.assertEqual( a1.a11_s(0x7fffffff), -1 )
|
||||
self.assertEqual( a1.a11_us(0x70000000), 0 )
|
||||
self.assertEqual( a1.a11_us(0x7fffffff), 65535 )
|
||||
self.assertEqual( a1.a11_i(-0x80000000), -2147483648 )
|
||||
self.assertEqual( a1.a11_l(-0x80000000), -2147483648 )
|
||||
self.assertEqual( a1.a11_ll(-0x80000000), -2147483648 )
|
||||
self.assertEqual( a1.a11_ui(0xffffffff), 4294967295 )
|
||||
self.assertEqual( a1.a11_ul(0xffffffff), 4294967295 )
|
||||
self.assertEqual( a1.a11_ull(0xffffffff), 4294967295 )
|
||||
if "a10_d_qstr" in a1.__dict__:
|
||||
self.assertEqual( a1.a10_d_qstr(5.25), "5.25" )
|
||||
self.assertEqual( a1.a10_d_qstrref(5.2), "5.2" )
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ class DBLayoutToNetlistTests(unittest.TestCase):
|
|||
|
||||
lvs = pya.LayoutVsSchematic()
|
||||
|
||||
infile = os.path.join(ut_testsrc, "testdata", "algo", "lvs_test1b_au.lvsdb")
|
||||
infile = os.path.join(ut_testsrc, "testdata", "algo", "lvsdb_read_test.lvsdb")
|
||||
lvs.read(infile)
|
||||
|
||||
tmp = os.path.join(ut_testtmp, "tmp.lvsdb")
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ class DBLayoutToNetlistTests(unittest.TestCase):
|
|||
xref = pya.NetlistCrossReference()
|
||||
|
||||
lvs = pya.LayoutVsSchematic()
|
||||
infile = os.path.join(ut_testsrc, "testdata", "algo", "lvs_test1b_au.lvsdb")
|
||||
infile = os.path.join(ut_testsrc, "testdata", "algo", "lvsdb_read_test.lvsdb")
|
||||
lvs.read(infile)
|
||||
|
||||
reader = pya.NetlistSpiceReader()
|
||||
|
|
@ -79,7 +79,7 @@ class DBLayoutToNetlistTests(unittest.TestCase):
|
|||
ut_testsrc = os.getenv("TESTSRC")
|
||||
|
||||
lvs = pya.LayoutVsSchematic()
|
||||
input = os.path.join(ut_testsrc, "testdata", "algo", "lvs_test2b_au.lvsdb")
|
||||
input = os.path.join(ut_testsrc, "testdata", "algo", "lvsdb_read_test2.lvsdb")
|
||||
lvs.read(input)
|
||||
|
||||
xref = lvs.xref()
|
||||
|
|
|
|||
|
|
@ -308,6 +308,27 @@ class Basic_TestClass < TestBase
|
|||
assert_equal( a2.a1, 11 )
|
||||
assert_equal( a3.a1, -11 )
|
||||
|
||||
assert_equal( a1.a10_s(0x70000000), "0" )
|
||||
assert_equal( a1.a10_s(0x7fffffff), "-1" )
|
||||
assert_equal( a1.a10_us(0x70000000), "0" )
|
||||
assert_equal( a1.a10_us(0x7fffffff), "65535" )
|
||||
assert_equal( a1.a10_i(-0x80000000), "-2147483648" )
|
||||
assert_equal( a1.a10_l(-0x80000000), "-2147483648" )
|
||||
assert_equal( a1.a10_ll(-0x80000000), "-2147483648" )
|
||||
assert_equal( a1.a10_ui(0xffffffff), "4294967295" )
|
||||
assert_equal( a1.a10_ul(0xffffffff), "4294967295" )
|
||||
assert_equal( a1.a10_ull(0xffffffff), "4294967295" )
|
||||
assert_equal( a1.a11_s(0x70000000), 0 )
|
||||
assert_equal( a1.a11_s(0x7fffffff), -1 )
|
||||
assert_equal( a1.a11_us(0x70000000), 0 )
|
||||
assert_equal( a1.a11_us(0x7fffffff), 65535 )
|
||||
assert_equal( a1.a11_i(-0x80000000), -2147483648 )
|
||||
assert_equal( a1.a11_l(-0x80000000), -2147483648 )
|
||||
assert_equal( a1.a11_ll(-0x80000000), -2147483648 )
|
||||
assert_equal( a1.a11_ui(0xffffffff), 4294967295 )
|
||||
assert_equal( a1.a11_ul(0xffffffff), 4294967295 )
|
||||
assert_equal( a1.a11_ull(0xffffffff), 4294967295 )
|
||||
|
||||
assert_equal( a1.a10_d(5.2), "5.2" )
|
||||
if a1.respond_to?(:a10_d_qstr)
|
||||
assert_equal( a1.a10_d_qstr(5.25), "5.25" )
|
||||
|
|
|
|||
|
|
@ -146,7 +146,7 @@ class DBLayoutVsSchematic_TestClass < TestBase
|
|||
|
||||
lvs = RBA::LayoutVsSchematic::new
|
||||
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvs_test1b_au.lvsdb")
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvsdb_read_test.lvsdb")
|
||||
lvs.read(input)
|
||||
|
||||
tmp = File::join($ut_testtmp, "tmp.lvsdb")
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ class DBNetlistCrossReference_TestClass < TestBase
|
|||
xref = RBA::NetlistCrossReference::new
|
||||
|
||||
lvs = RBA::LayoutVsSchematic::new
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvs_test1b_au.lvsdb")
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvsdb_read_test.lvsdb")
|
||||
lvs.read(input)
|
||||
|
||||
reader = RBA::NetlistSpiceReader::new
|
||||
|
|
@ -54,7 +54,7 @@ class DBNetlistCrossReference_TestClass < TestBase
|
|||
def test_2_CircuitPairs
|
||||
|
||||
lvs = RBA::LayoutVsSchematic::new
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvs_test2b_au.lvsdb")
|
||||
input = File.join($ut_testsrc, "testdata", "algo", "lvsdb_read_test2.lvsdb")
|
||||
lvs.read(input)
|
||||
|
||||
xref = lvs.xref
|
||||
|
|
|
|||
|
|
@ -695,6 +695,8 @@ class RDB_TestClass < TestBase
|
|||
assert_equal(view.num_rdbs, 2)
|
||||
assert_equal(ot, 0)
|
||||
|
||||
mw.close_current_view
|
||||
|
||||
end
|
||||
|
||||
# scan_... methods
|
||||
|
|
|
|||
|
|
@ -3,34 +3,40 @@
|
|||
# environment is shut down. Therefore we must release all RBA objects by explicitly calling the GC
|
||||
# and start the test suite manually.
|
||||
|
||||
err = 0
|
||||
any = nil
|
||||
repeat = (ENV["TESTREPEAT"] || "1").to_i
|
||||
begin
|
||||
|
||||
class MyTestRunner < Test::Unit::UI::Console::TestRunner
|
||||
def initialize(suite, *args)
|
||||
super(suite, *args)
|
||||
end
|
||||
def test_started(name)
|
||||
super
|
||||
end
|
||||
end
|
||||
err = 0
|
||||
any = nil
|
||||
repeat = (ENV["TESTREPEAT"] || "1").to_i
|
||||
|
||||
Object.constants.each do |c|
|
||||
if c.to_s =~ /_TestClass$/
|
||||
repeat.times do
|
||||
r = MyTestRunner::new(Object.const_get(c)).start
|
||||
err += r.error_count + r.failure_count
|
||||
class MyTestRunner < Test::Unit::UI::Console::TestRunner
|
||||
def initialize(suite, *args)
|
||||
super(suite, *args)
|
||||
end
|
||||
def test_started(name)
|
||||
super
|
||||
end
|
||||
any = true
|
||||
end
|
||||
end
|
||||
|
||||
if !any
|
||||
raise("No test class defined (any ending with _TestClass)")
|
||||
end
|
||||
|
||||
if err > 0
|
||||
raise("Tests failed (#{err} Errors + Failures)")
|
||||
|
||||
Object.constants.each do |c|
|
||||
if c.to_s =~ /_TestClass$/
|
||||
repeat.times do
|
||||
r = MyTestRunner::new(Object.const_get(c)).start
|
||||
err += r.error_count + r.failure_count
|
||||
end
|
||||
any = true
|
||||
end
|
||||
end
|
||||
|
||||
if !any
|
||||
raise("No test class defined (any ending with _TestClass)")
|
||||
end
|
||||
|
||||
if err > 0
|
||||
raise("Tests failed (#{err} Errors + Failures)")
|
||||
end
|
||||
|
||||
ensure
|
||||
GC.start
|
||||
end
|
||||
|
||||
|
|
|
|||
|
|
@ -35,3 +35,6 @@ Object.constants.each do |c|
|
|||
end
|
||||
end
|
||||
|
||||
# Some cleanup ahead
|
||||
GC.start
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue