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136 Commits

Author SHA1 Message Date
steve c4e069e505 Handle adders that use Cout for the top bit. 2003-10-31 03:45:50 +00:00
steve 89fca07dc8 Add the iverilog-fpga man page. 2003-10-27 06:12:47 +00:00
steve 1b8034818c Emit constants for LPM device. 2003-10-27 02:18:27 +00:00
steve fea68f7fe7 Support synchronous set of LPM_FF devices. 2003-09-03 23:34:09 +00:00
steve 14150d6fba ifdef idents correctly. 2003-08-26 16:26:01 +00:00
steve 816aba993f iverilog-vpi support --cflags a la gtk. 2003-08-26 04:45:47 +00:00
steve ec07674d40 Fix Makefiles to support read-only source directory. 2003-08-22 04:27:10 +00:00
steve e561819179 Add synthesis support for synchronous reset. 2003-08-15 02:23:52 +00:00
steve b6c3f94d52 Add async clear to LPM_FF devices. 2003-08-10 16:42:23 +00:00
steve a95463ff81 Add support for IVL_LPM_MULT device. 2003-08-09 03:23:03 +00:00
steve fbe6fc315b Generate LPM_FF devices. 2003-08-09 02:40:50 +00:00
steve 63fb5ea03c Add support for OR/NOR/bufif0/bufif1. 2003-08-07 05:18:04 +00:00
steve 800e9dd76a Add arch=lpm to the documentation. 2003-08-07 05:17:34 +00:00
steve f4b8a4877f Add an LPM device type. 2003-08-07 04:04:01 +00:00
steve 5b351599f0 Allow attributes on Verilog 2001 port declarations. 2003-07-04 03:57:18 +00:00
steve c2feb162f2 PAD attribute can be used to assign pins. 2003-07-04 01:08:03 +00:00
steve 7734ba99fc Generate MUXF5 based 4-input N-wide muxes. 2003-07-04 00:10:09 +00:00
steve 272dc749da IOPAD support. 2003-07-03 17:46:33 +00:00
steve eb605694eb More xilinx common code. 2003-07-02 03:02:15 +00:00
steve b810556d3f Remember to set INIT on wide-or trailing luts. 2003-07-02 02:58:18 +00:00
steve 3a3e288f6f No longer export generic-edif functions. 2003-07-02 00:48:03 +00:00
steve 0ffb613229 Missing copyright notice. 2003-07-02 00:27:24 +00:00
steve 2e4276f5c5 Fix spelling of part= flag. 2003-07-02 00:26:49 +00:00
steve daad030ce6 Add xilinx support for bufif1. 2003-07-02 00:25:40 +00:00
steve 5314ec373b lut3 for 3input wide or. 2003-06-30 19:21:21 +00:00
steve 03089bdbf3 Add support for wide OR/NOR gates. 2003-06-28 04:18:47 +00:00
steve 253f3bc660 Add Xilinx support for A/B MUX devices. 2003-06-26 03:57:05 +00:00
steve 0e797dc7bc Virtex and Virtex2 share much code. 2003-06-25 02:55:57 +00:00
steve f7162eb538 Spelling fixes. 2003-06-25 01:49:06 +00:00
steve 957a464743 Virtex support for NOT gates. 2003-06-25 01:46:44 +00:00
steve 79248d0592 Add ivl_synthesis_cell support for virtex2. 2003-06-24 03:55:00 +00:00
steve 536b79b667 Handle bufz as buf in generic fpga/edif target. 2003-06-17 03:47:41 +00:00
steve d5642e6bdf Preserve user specifiec CFLAGS/CPPFLAGS. 2003-04-23 05:27:44 +00:00
steve aad7816949 Move library cell management to common file. 2003-04-05 05:53:34 +00:00
steve 15fa7246f2 Fix LUT function for chained NE. 2003-04-05 01:35:40 +00:00
steve 882c46437c Add == and some lut logic. 2003-04-04 06:20:29 +00:00
steve 6495d0bd5d Add xlibrary celltable. 2003-04-04 04:59:03 +00:00
steve 9531aafaf2 Wide shift of MUX was wrong. 2003-03-31 01:34:19 +00:00
steve aa9ab7e09c Fix wrong input constant to bottom of GE. 2003-03-31 00:25:19 +00:00
steve 2be1b1a096 Proper sliced >= comparator. 2003-03-31 00:04:21 +00:00
steve 3878f3c770 Handle wide ports of macros. 2003-03-30 03:43:44 +00:00
steve a49df16d44 Give proper basenames to PAD signals. 2003-03-24 02:29:04 +00:00
steve 004b377701 Document the virtex2 architecture. 2003-03-24 02:28:38 +00:00
steve ff032fa18c Add new virtex2 architecture family, and 
also the new edif.h EDIF management functions.
 2003-03-24 00:47:54 +00:00
steve feee40603c Makefile cleanups to better support concurrent make. 2003-02-27 22:13:22 +00:00
steve 9ceaaa5faf ivl_lpm_name is obsolete. 2003-02-26 01:24:35 +00:00
steve 751e4e4c79 Fix instanceRef spelling. 2002-11-24 02:26:14 +00:00
steve 9a3c9507ed Handle wide AND/NOR devices with Virtex carry logic. 2002-11-22 05:46:06 +00:00
steve d71d52bfe9 Implement bufif1 as BUFT 2002-11-22 01:45:40 +00:00
steve b4e8ea5a0c Install shared objects as programs, not data. 2002-11-05 02:14:41 +00:00
steve fe6756eb07 Fix bottom bit of ADD/SUB device. 2002-11-01 02:36:34 +00:00
steve 539e494bc0 Give nets better names, if available. 2002-11-01 02:36:22 +00:00
steve 1298656c22 Fix up left shift to pass compile, 
fix up ADD/SUB to generate missing pieces,
 Add the asynch set/reset to DFF devices.
 2002-10-30 03:58:45 +00:00
steve ae27165ffe Add Virtex code generators for left shift, 
subtraction, and GE comparators.
 2002-10-28 02:05:56 +00:00
steve 9f1ce170e6 Generate code for 8:1 muxes msing F5 and F6 muxes. 2002-09-15 21:52:19 +00:00
steve 327c8826f4 Generate Virtex code for 4:1 mux slices. 2002-09-14 05:19:19 +00:00
steve 52bf4e613f conditional ident string using autoconfig. 2002-08-12 01:34:58 +00:00
steve 774f78cd3e Autoconfig ident support. 2002-08-12 00:27:10 +00:00
steve aca1dcf848 Add missing Log and Ident strings. 2002-08-11 23:47:04 +00:00
steve d126a414bd Spelling errors. 2002-04-30 04:26:42 +00:00
steve 54bb59ae99 Support compile on MacosX 10.1.1 (Timothy J. Wood) 2001-11-17 17:57:58 +00:00
steve cc5ddc0b6b MacOSX 10.1 updates. 2001-11-04 05:03:21 +00:00
steve 36d36d99f3 Generate BUF devices for bufz logic. 2001-10-11 00:12:28 +00:00
steve cbd501b865 Fix some Cygwin DLL handling. (Venkat Iyer) 2001-09-30 16:45:10 +00:00
steve a73cfbc2b5 MacOS X compile time changes. (Timothy Wood) 2001-09-20 03:21:01 +00:00
steve 606eb2b3cd Support the cellref attribute. 2001-09-16 22:26:47 +00:00
steve cefbb635c1 Suppor the PAD attribute on signals. 2001-09-16 01:48:16 +00:00
steve b2b8b89cd8 Make configure detect malloc.h 2001-09-15 18:27:04 +00:00
steve 92760f2c5f Support != in virtex code generator. 2001-09-15 05:06:04 +00:00
steve 9fda809fa6 Add XOR and XNOR gates. 2001-09-14 04:17:20 +00:00
steve 5976e7078c Xilinx uses GROUND and VCC as pin names for the 
GND and VCC devices.

 Connect the top end of the EQ chain to the MUXCY
 instead of to the LUT. The MUXCY has the real output.
 2001-09-12 04:35:25 +00:00
steve da9a84ed84 Use carry mux to implement wide identity compare, 
Place property item in correct place in LUT cell list.
 2001-09-11 05:52:31 +00:00
steve 167f94bdbf Add 4 wide identity compare. 2001-09-10 03:48:34 +00:00
steve 4507351d48 Virtex support for mux devices and adders 
with carry chains. Also, make Virtex specific
 implementations of primitive logic.
 2001-09-09 22:23:28 +00:00
steve acde444439 Separate the virtex and generic-edif code generators. 2001-09-06 04:28:39 +00:00
steve 298a352cbd Add documentation for the code generator. 2001-09-02 23:58:49 +00:00
steve 356552faad Add virtex support for some basic logic, the DFF 
and constant signals.
 2001-09-02 23:53:55 +00:00
steve 5e1e79b3c4 Rearrange the XNF code generator to be generic-xnf 
so that non-XNF code generation is also possible.

 Start into the virtex EDIF output driver.
 2001-09-02 21:33:07 +00:00
steve 2996d2eb19 Generic ADD code. 2001-09-01 04:30:44 +00:00
steve 16023cbbd6 Generate code for MUX devices. 2001-09-01 02:28:42 +00:00
steve 77927972e5 identity compare, and PWR records for constants. 2001-09-01 02:01:30 +00:00
steve 8b8a3d83e0 Relax pin count restriction on logic gates. 2001-08-31 23:02:13 +00:00
steve c1c88f87c6 Many more logic gate types. 2001-08-31 04:17:56 +00:00
steve a9b5c9c037 Add root port SIG records. 2001-08-31 02:59:06 +00:00
steve a3c3019a04 Mangle nexus names. 2001-08-30 04:31:04 +00:00
steve f063bf833f Add the fpga target. 2001-08-28 04:14:20 +00:00