 Bugra Onal
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a361d9f7bb
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Fixed write_size checks for None
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2022-07-28 16:45:58 -07:00 |
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Bugra Onal
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6efe974d7b
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Delete sram_base form rebase
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2022-07-28 16:02:39 -07:00 |
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Bugra Onal
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9771bb7056
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Don't generate wmask and if word per line is 1
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2022-07-28 15:59:28 -07:00 |
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Bugra Onal
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02d8eca640
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Fix indentation
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2022-07-28 15:07:19 -07:00 |
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Bugra Onal
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36e23dc80f
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Moved template module to new modules folder
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2022-07-28 15:05:34 -07:00 |
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Bugra Onal
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3f1a5a2051
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Shrunk address register in multibank verilog
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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5f45f7db15
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Fixed the bad commas with post-process regex
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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a75951b5b1
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write_size init in sram_config
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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898a1f07f5
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Fixed verilog filename double extension
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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c1e891b2fb
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Multibank file generation (messy)
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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846dfc79dc
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modified template engine & sram multibank class
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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30f5638b9f
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Replaced instances of addr_size with bank_addr
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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29079bd6ac
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Added conditional sections to template
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2022-07-28 15:03:41 -07:00 |
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Bugra Onal
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24bb6f8c11
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Multibank file generation (messy)
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2022-07-28 15:03:37 -07:00 |
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 samuelkcrow
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1c8aeaa68a
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fix imports
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2022-07-27 11:09:10 -07:00 |
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samuelkcrow
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2ff9ea4f78
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move generic functions from control_logic module to new control_logic_base module
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2022-07-26 23:22:02 -07:00 |
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 mrg
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69d5731d67
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2022-07-22 13:47:19 -07:00 |
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samuelkcrow
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b82213caff
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use packages for imports in modules
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2022-07-22 12:56:47 -07:00 |
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 Eren Dogan
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e3fe8c3229
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Remove line ending whitespace
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2022-07-22 19:52:38 +03:00 |
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samuelkcrow
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5fa0689c02
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fix drc error in wlen_row
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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08ac1c176a
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connect in pin via m2 instead of m3, passes lvs now
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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12c58b0457
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use spice names for delay chain output pins in layout
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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73021be8eb
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copy vertical bus spacing from control_logic.py
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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2611468dd7
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replace route_supply with route supplies from control_logic.py
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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9182ad7c61
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add m4 spacing for route_rails same as control_logic.py
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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7f52e63aca
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route glitch3 to inverter on wen row
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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231dca5b51
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route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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74bf3770d9
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move pins to m3, route in pin down to avoid m3 collision
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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fd7a7c2564
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routing mistake in route_wlen
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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1e1ec54275
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fix indentation errors, typos, and missing iterator
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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3526a57864
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don't route rbl to conrol logic
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2022-07-21 19:35:02 -07:00 |
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samuelkcrow
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1d6bd78612
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multi-delay layout pins and routing for them in control logic
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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d7b1368115
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all route functions except for delay
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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63ea1588c1
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more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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0a3c1dd9b8
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remove pre_sen entirely, move inverter to wl_en row, complete placement functions
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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7b4af87fda
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remove the cs_buf function call... smh
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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5edb511dab
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try it without pre_sen
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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71f241f660
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remove remaining cs_buf functions
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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67c1560df0
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forgot other place with cs_buf
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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fede082b80
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cs instead of cs_buf now that everything else is working
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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30b9c2fc25
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remove glitch inverters from placement functions, move glitch1 to pen row
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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606260dd68
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use odd number inverter chains from delay chain for delay instead of external inverters
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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b9b57ab6b3
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double length of delay chain as well
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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06254fae72
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forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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ef2c9fe296
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exclude rbl connection in sram base for delay control logic
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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7d4b718344
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add most functions needed for delay control logic, fix multi-delay pin order issue
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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45239ca2a9
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use cs_buf for sense amp on r ports instead of cs
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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c4138c9f9b
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typo in cs buf netlist function
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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2b72fbee4e
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bug fix list vs set
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2022-07-21 19:35:01 -07:00 |
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samuelkcrow
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11ea82e782
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check delay chain pinout list, add cs_buf to control logic
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2022-07-21 19:35:01 -07:00 |
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