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OpenRAM
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1098 Commits

Author SHA1 Message Date
Bugra Onal 6af9c556a9 Fix char tests 2023-04-19 12:41:39 -07:00
Eren Dogan 51ddb08385 Enable sky130 regression but disable failing tests 2023-04-13 22:12:46 -07:00
Bugra Onal dae275c508 Merge branch 'dev' into char 2023-04-12 12:00:31 -07:00
Sam Crow eea748ff3e remove test for unsupported config 2023-04-10 11:16:10 -07:00
Sam Crow 670b40642b add no rbl tests to 15 global array tests 2023-04-10 10:38:52 -07:00
Sam Crow dff94a032e fix bug in right rbl dual port replica array test 2023-04-07 11:30:15 -07:00
Sam Crow 83b25138d0 apply 14* standard to 15_local tests 2023-04-03 10:11:49 -07:00
Sam Crow 9181f6a218 standardize 14* test structure 2023-04-03 10:08:57 -07:00
Jacob Walker 0b056dca54 fixed rom bank test name 2023-03-30 18:44:55 -07:00
mrg 7c453e80be Simplify ROM test. 2023-03-30 11:30:50 -07:00
mrg af0a6d32fb Remove old skip tests 2023-03-30 11:30:50 -07:00
mrg 2075d244cb Change ROM test permissions to include x 2023-03-30 11:30:50 -07:00
mrg d2b5be0130 Add exclude tests for ROMs 2023-03-30 11:30:50 -07:00
mrg fe65a20431 Rename ROM unit tests. 2023-03-30 11:30:50 -07:00
Jacob Walker eec0f02bb8 skip test file 2023-03-30 11:30:50 -07:00
Jacob Walker b50ec272da updated top level rom unit tests 2023-03-30 11:30:50 -07:00
Jacob Walker 382c91f342 precharge array test passing sky130 2023-03-30 11:30:50 -07:00
Jacob Walker 0cb4459b4b changed ROM test data path 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker 79efff9ca6 code cleanup and updated copyright 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
SWalker 764601a721 added binning to precharge pmos 2023-03-30 11:30:50 -07:00
Jesse Cirimelli-Low 6981cfa58b add example of writing out simulation netlist 2023-03-30 11:30:50 -07:00
Jacob Walker 736bd51fe1 add top level pins for sim 2023-03-30 11:30:50 -07:00
Jacob Walker 16df8e0e43 fixing decoder lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 559300e5cc taps in main array and decoder 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
Jacob Walker ce8197d206 pitch match decoder and array 2023-03-30 11:30:50 -07:00
Jacob Walker e697efa5f6 fixed base array lvs 2023-03-30 11:30:50 -07:00
Jacob Walker b2631b60ff updated imports to match upstream dev openram 2023-03-30 11:30:50 -07:00
Jacob Walker 63925bd48e Decoder array and start of rom bank 2023-03-30 11:30:50 -07:00
Jacob Walker bc8d564dbf array with poly straps passing drc/lvs 2023-03-30 11:30:50 -07:00
Jacob Walker 7309af7e29 base and dummy array alignment in sky130 2023-03-30 11:30:50 -07:00
Jacob Walker d7ac26a053 array generation and bitline routing with array module 2023-03-30 11:30:50 -07:00
Jacob Walker 4db5c3be26 basic nmos array, for nand rom 2023-03-30 11:30:50 -07:00
Sam Crow 299512eba2 standardize array tests 2023-03-22 18:56:52 -07:00
Eren Dogan 6eebef8c72 Fix typo in Makefile 2023-03-16 14:40:24 -07:00
mrg 8ea100b52e Split pbitcell tests to fix factory.reset() bug. 2023-03-14 08:50:00 -07:00
Eren Dogan 16490e9928 Merge branch 'conda' into dev 2023-03-13 16:10:35 -07:00
Eren Dogan 650b6e513c Remove the hack used for unit tests running on docker 2023-03-10 16:35:22 -08:00
mrg c9bf3c1261 Remove factory.reset from all unit tests as we no longer use regress.py. 2023-03-10 10:44:54 -08:00
Sam Crow 710f0fbae5 update local/global tests for no rbls 2023-03-09 14:37:07 -08:00
Sam Crow 7abaf0463e create no rbl no dummy tests 2023-03-09 10:05:17 -08:00
mrg 5c173551ec Remove regress.py and skip_tests for Makefile option instead. 2023-03-02 12:44:52 -08:00
mrg 1f3bdd598a Add scn4m_subm global array test to skip test until issue is fixed. 2023-03-01 14:23:31 -08:00
mrg 49dbbb33bc Add skip tests until inverters added to sense amps. 2023-03-01 14:15:07 -08:00
Bugra Onal 613146520e Merge branch 'library' into char 2023-02-23 15:11:39 -08:00
samuelkcrow e90964fbda update copyright 2023-02-21 14:04:31 -08:00
Bugra Onal 8650315179 Updated copyright headers 2023-02-21 13:52:21 -08:00
Bugra Onal 6bdcdb8f37 Merge branch 'dev' into char 2023-02-21 13:00:47 -08:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
Eren Dogan b37711e643 Merge branch 'dev' into deploy_pip 2023-02-20 14:08:20 -08:00
Bugra Onal 3b69cafde7 Update Xyce char tests 2023-02-17 19:15:14 -08:00
mrg c07268d297 Disable power routing on some freepdk45 tests for issue 36 2023-02-17 17:00:04 -08:00
Eren Dogan d8a169e79f Reenable tests 2023-02-17 14:56:52 -08:00
Eren Dogan d3da632dc1 Fix typo in model delay test 2023-02-17 13:34:02 -08:00
Eren Dogan a7582c05dc Disable failing tests 2023-02-17 10:42:31 -08:00
Bugra Onal 9002a8ac70 Merge branch 'dev' into char 2023-02-14 15:05:27 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow cc408447b1 standardize names and content of tests in the 14_* group 2023-01-26 14:14:25 -08:00
Eren Dogan c613693399 Don't use Docker for unit tests 2023-01-22 18:19:56 -08:00
Bugra Onal a7cbf254be Merge branch 'dev' into char 2023-01-19 12:18:38 -08:00
samuelkcrow 78cabf9ca3 make capped array name more descriptive and add x mode to tests 2023-01-17 10:20:16 -08:00
samuelkcrow f651b484c5 fix capped array tests after dev merge 2022-12-14 08:48:12 -08:00
samuelkcrow 6a8a76dd23 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into no_rbl 2022-12-14 08:13:08 -08:00
Eren Dogan fe81bbfd7e Fix paths in library usage tests 2022-12-02 20:28:14 -08:00
Eren Dogan 6a4f6cbbed Move sram and sram_config to openram namespace 2022-12-02 15:28:06 -08:00
Eren Dogan fe0826d07c Add unit tests for library usage 2022-12-02 13:04:54 -08:00
Eren Dogan b40a17f4a5 Fix log file for sram_compiler tests 2022-12-02 13:00:12 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Bugra Onal b9f16ea490 Merge branch 'dev' into char 2022-11-29 14:50:00 -08:00
Eren Dogan a37d41b406 Fix typo 2022-11-27 16:41:28 -08:00
Eren Dogan 316f75861b Fix unit tests running on docker with a hack for now 2022-11-27 14:32:55 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Eren Dogan e718106d87 Change is_unit_test to False by default 2022-11-21 14:52:57 -08:00
Eren Dogan 845f32805f Change compiler name for unit tests 2022-11-06 14:05:08 -08:00
mrg b1a88d8c8a Remove variable reference in ifdef 2022-11-02 08:02:22 -07:00
mrg aeca2c6b88 Allow any definition of KEEP to keep temp files 2022-10-20 14:31:26 -07:00
Bugra Onal 2b79646b8f Merge branch 'dev' into char 2022-10-04 09:09:52 -07:00
samuelkcrow 8bc3903a04 remove end caps from replica column (will not pass sky130 drc) 2022-09-26 14:23:09 -07:00
samuelkcrow 37dee02161 Merge branch 'dev' into no_rbl 2022-09-13 12:34:57 -07:00
samuelkcrow 004ee3748d add option to keep tmp files when running tests with make 2022-09-08 13:40:48 -07:00
samuelkcrow fe0cfac6c8 tests for new capped array module 2022-09-07 12:39:01 -07:00
Bugra Onal 1a214a7309 Fixed utest 25 golden 2022-08-30 09:17:51 -07:00
Bugra Onal 56879bf48b Cleanup 2022-08-18 20:35:34 -07:00
Bugra Onal c0c15537d9 Added golden files for freepdk test 25 2022-08-18 11:04:53 -07:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal b33c2ab96c Fixed test 25 golden files 2022-08-12 21:33:40 -07:00
Bugra Onal 623c1ac02f Convert unit test 25 to new modules convert 2022-08-10 16:33:50 -07:00
Bugra Onal c7975e3274 Use fake sram in memchar 2022-08-10 12:22:47 -07:00
Bugra Onal 2101067e4a Characterizer options 2022-08-10 12:22:47 -07:00
samuelkcrow 8872a3e312 add tests 2022-08-10 12:22:47 -07:00
Bugra Onal caac39c88b Added 1bank module check to the multibank test 2022-07-28 15:03:41 -07:00
Bugra Onal 3f1a5a2051 Shrunk address register in multibank verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 6b5fe8a096 Changed test name for multibank verilog test 2022-07-28 15:03:41 -07:00
Bugra Onal 8f00e396cd Added unit test for multibank 2022-07-28 15:03:41 -07:00
Bugra Onal a87b40e1cb Added conditional sections to template 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal 29079bd6ac Added conditional sections to template 2022-07-28 15:03:41 -07:00