Merge branch 'dev' into char

.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,27 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**Version**
+Which commit are you using?
+
+**To Reproduce**
+What did you do to demonstrate the bug?
+Please include your configuration file used.
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Logs**
+If applicable, add logs or output to help explain your problem.
+
+**Additional context**
+Add any other context about the problem here.

.gitignore

@@ -21,3 +21,4 @@ sky130A/
 sky130B/
 skywater-pdk/
 sky130_fd_bd_sram/
+docker/openram-ubuntu.log

Makefile

@@ -58,16 +58,14 @@ $(SKY130_PDKS_DIR): check-pdk-root
 	@echo "Cloning skywater PDK..."
 	@[ -d $(PDK_ROOT)/skywater-pdk ] || \
 		git clone https://github.com/google/skywater-pdk.git $(PDK_ROOT)/skywater-pdk
-	@cd $(SKY130_PDKS_DIR) && \
-		git checkout main && git pull && \
-		git checkout -qf $(SKY130_PDKS_GIT_COMMIT) && \
-		git submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
+	@git -C $(SKY130_PDKS_DIR) checkout $(SKY130_PDKS_GIT_COMMIT) && \
+		git -C $(SKY130_PDKS_DIR) submodule update --init libraries/sky130_fd_pr/latest libraries/sky130_fd_sc_hd/latest
 
 $(OPEN_PDKS_DIR): $(SKY130_PDKS_DIR)
 	@echo "Cloning open_pdks..."
 	@[ -d $(OPEN_PDKS_DIR) ] || \
 		git clone $(OPEN_PDKS_GIT_REPO) $(OPEN_PDKS_DIR)
-	@cd $(OPEN_PDKS_DIR) && git pull && git checkout $(OPEN_PDKS_GIT_COMMIT)
+	@git -C $(OPEN_PDKS_DIR) checkout $(OPEN_PDKS_GIT_COMMIT)
 
 $(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR)
 	@echo "Installing open_pdks..."
@@ -80,9 +78,9 @@ $(SKY130_PDK): $(OPEN_PDKS_DIR) $(SKY130_PDKS_DIR)
 
 $(SRAM_LIB_DIR): check-pdk-root
 	@echo "Cloning SRAM library..."
-	@[ -d $(SRAM_LIB_DIR) ] || (\
-		git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR) && \
-		cd $(SRAM_LIB_DIR) && git pull && git checkout $(SRAM_LIB_GIT_COMMIT))
+	@[ -d $(SRAM_LIB_DIR) ] || \
+		git clone $(SRAM_LIB_GIT_REPO) $(SRAM_LIB_DIR)
+	@git -C $(SRAM_LIB_DIR) checkout $(SRAM_LIB_GIT_COMMIT)
 
 install: $(SRAM_LIB_DIR)
 	@[ -d $(PDK_ROOT)/sky130A ] || \
@@ -226,5 +224,5 @@ build-library:
 
 # Build and install the openram library
 library: build-library
-	@python3 -m pip install --find-links=dist openram --force
-.PHONY: library
+	@python3 -m pip install --force --find-links=dist openram
+.PHONY: library

README.md

@@ -44,12 +44,14 @@ OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
 
 # Publications
 
-+ M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016
-+ S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.
-+ E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017
-+ B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization",  IEEE International Symposium on Circuits and Systems (ISCAS), 2019
-+ B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019
-+ H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019
++ [M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016.](https://escholarship.org/content/qt8x19c778/qt8x19c778_noSplash_b2b3fbbb57f1269f86d0de77865b0691.pdf)
++ [S. Ataei, J. Stine, M. Guthaus, “A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS,” International Conference on Computer Design (ICCD), 2016, pp. 499-506.](https://escholarship.org/uc/item/99f6q9c9)
++ [E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017.](https://escholarship.org/content/qt7nn0j5x3/qt7nn0j5x3_noSplash_172457455e1aceba20694c3d7aa489b4.pdf)
++ [B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization",  IEEE International Symposium on Circuits and Systems (ISCAS), 2019.](https://escholarship.org/content/qt98s4c1hp/qt98s4c1hp_noSplash_753dcc3e218f60aafff98ef77fb56384.pdf)
++ [B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://ieeexplore.ieee.org/document/8920325)
++ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
++ [H. Nichols, "Statistical Modeling of SRAMs", M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
++ [M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software", IEEE International Electron Devices Meeting (IEDM), 2020.](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9372047)
 
  
 # Contributors & Acknowledgment

__init__.py

@@ -1,22 +1,31 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import os
-import sys
 
 # Attempt to add the source code to the PYTHONPATH here before running globals.init_openram().
 try:
     OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
 except:
-    import openram
-    OPENRAM_HOME = os.path.dirname(openram.__file__) + "/compiler"
+    OPENRAM_HOME = os.path.dirname(os.path.abspath(__file__)) + "/compiler"
 
 if not os.path.isdir(OPENRAM_HOME):
     assert False
 
-if OPENRAM_HOME not in sys.path:
-    sys.path.insert(0, OPENRAM_HOME)
+# Make sure that OPENRAM_HOME is an environment variable just in case
+if "OPENRAM_HOME" not in os.environ.keys():
+    os.environ["OPENRAM_HOME"] = OPENRAM_HOME
+
+# Prepend $OPENRAM_HOME to __path__ so that openram will use those modules
+__path__.insert(0, OPENRAM_HOME)
+
+# Import everything in globals.py
+from .globals import *
+# Import classes in the "openram" namespace
+# sram_config should be imported before sram
+from .sram_config import *
+from .sram import *

compiler/base/__init__.py

@@ -1,3 +1,8 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 from .channel_route import *
 from .contact import *
 from .delay_data import *

compiler/base/channel_route.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import collections
-import debug
-from tech import drc
+from openram import debug
+from openram.tech import drc
 from .vector import vector
 from .design import design
 
@@ -405,4 +405,3 @@ class channel_route(design):
                                       to_layer=self.horizontal_layer,
                                       offset=pin_pos)
 
-

compiler/base/contact.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
+from openram.tech import drc, layer, preferred_directions
+from openram.tech import layer as tech_layers
 from .hierarchy_design import hierarchy_design
 from .vector import vector
-from tech import drc, layer, preferred_directions
-from tech import layer as tech_layers
 
 
 class contact(hierarchy_design):

compiler/base/delay_data.py

@@ -1,12 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 
-
 class delay_data():
     """
     This is the delay class to represent the delay information
@@ -38,7 +37,3 @@ class delay_data():
         assert isinstance(other, delay_data)
         return delay_data(other.delay + self.delay,
                           self.slew)
-
-
-
-

compiler/base/design.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, layer
-from tech import preferred_directions
-from tech import cell_properties as props
-from globals import OPTS
+from openram import debug
+from openram.tech import GDS, layer
+from openram.tech import preferred_directions
+from openram.tech import cell_properties as props
+from openram import OPTS
 from . import utils
 from .hierarchy_design import hierarchy_design
 
@@ -67,7 +67,7 @@ class design(hierarchy_design):
         self.setup_multiport_constants()
 
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             self.supply_stack = power_grid
         except ImportError:
             # if no power_grid is specified by tech we use sensible defaults

compiler/base/errors.py

@@ -1,4 +1,8 @@
-
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 
 class drc_error(Exception):
     """Exception raised for DRC errors.

compiler/base/geometry.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -8,14 +8,14 @@
 """
 This provides a set of useful generic types for the gdsMill interface.
 """
-import debug
-from .vector import vector
-import tech
 import math
 import copy
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .utils import round_to_grid
+from .vector import vector
 
 
 class geometry:
@@ -249,7 +249,6 @@ class instance(geometry):
         """ Return an absolute pin that is offset and transformed based on
         this instance location. Index will return one of several pins."""
 
-        import copy
         if index == -1:
             pin = copy.deepcopy(self.mod.get_pin(name))
             pin.transform(self.offset, self.mirror, self.rotate)
@@ -267,7 +266,6 @@ class instance(geometry):
         """ Return an absolute pin that is offset and transformed based on
         this instance location. """
 
-        import copy
         pin = copy.deepcopy(self.mod.get_pins(name))
 
         new_pins = []

compiler/base/hierarchy_design.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+import os
+from openram import debug
+from openram import OPTS
 from .hierarchy_layout import layout
 from .hierarchy_spice import spice
-import debug
-import os
-from globals import OPTS
 
 
 class hierarchy_design(spice, layout):
@@ -49,7 +49,7 @@ class hierarchy_design(spice, layout):
 
     def DRC_LVS(self, final_verification=False, force_check=False):
         """Checks both DRC and LVS for a module"""
-        import verify
+        from openram import verify
 
         # No layout to check
         if OPTS.netlist_only:
@@ -82,7 +82,7 @@ class hierarchy_design(spice, layout):
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.
@@ -102,7 +102,7 @@ class hierarchy_design(spice, layout):
 
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
-        import verify
+        from openram import verify
 
         # Unit tests will check themselves.
         # Do not run if disabled in options.

compiler/base/hierarchy_layout.py

@@ -1,32 +1,32 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
 import sys
+import os
 import re
 from math import sqrt
-import debug
-from gdsMill import gdsMill
-import tech
-from tech import drc, GDS
-from tech import layer as tech_layer
-from tech import layer_indices as tech_layer_indices
-from tech import preferred_directions
-from tech import layer_stacks as tech_layer_stacks
-from tech import active_stack as tech_active_stack
-from sram_factory import factory
-from globals import OPTS
+from openram import debug
+from openram.gdsMill import gdsMill
+from openram import tech
+from openram.tech import drc, GDS
+from openram.tech import layer as tech_layer
+from openram.tech import layer_indices as tech_layer_indices
+from openram.tech import preferred_directions
+from openram.tech import layer_stacks as tech_layer_stacks
+from openram.tech import active_stack as tech_active_stack
+from openram.sram_factory import factory
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 from .utils import round_to_grid
 from . import geometry
 
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
 
@@ -171,7 +171,7 @@ class layout():
         in many places in the compiler.
         """
         try:
-            from tech import power_grid
+            from openram.tech import power_grid
             layout.pwr_grid_layers = [power_grid[0], power_grid[2]]
         except ImportError:
             layout.pwr_grid_layers = ["m3", "m4"]
@@ -1253,7 +1253,6 @@ class layout():
 
     def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
         """ Add a three layer via structure. """
-        from sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1272,7 +1271,6 @@ class layout():
         Add a three layer via structure by the center coordinate
         accounting for mirroring and rotation.
         """
-        from sram_factory import factory
         via = factory.create(module_type="contact",
                              layer_stack=layers,
                              dimensions=size,
@@ -1379,10 +1377,10 @@ class layout():
 
     def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
         """Adds a ptx module to the design."""
-        import ptx
-        mos = ptx.ptx(width=width,
-                      mults=mults,
-                      tx_type=tx_type)
+        from openram.modules import ptx
+        mos = ptx(width=width,
+                  mults=mults,
+                  tx_type=tx_type)
         inst = self.add_inst(name=mos.name,
                              mod=mos,
                              offset=offset,
@@ -2176,7 +2174,6 @@ class layout():
 
         # Find the number of vias for this pitch
         supply_vias = 1
-        from sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,
@@ -2289,7 +2286,6 @@ class layout():
 
         # Find the number of vias for this pitch
         self.supply_vias = 1
-        from sram_factory import factory
         while True:
             c = factory.create(module_type="contact",
                                layer_stack=self.m1_stack,

compiler/base/hierarchy_spice.py

@@ -1,17 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import re
 import os
+import re
 import math
-import tech
-from globals import OPTS
+import textwrap as tr
 from pprint import pformat
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .delay_data import delay_data
 from .wire_spice_model import wire_spice_model
 from .power_data import power_data
@@ -37,7 +38,7 @@ class spice():
         # If we have a separate lvs directory, then all the lvs files
         # should be in there (all or nothing!)
         try:
-            from tech import lvs_name
+            from openram.tech import lvs_name
             lvs_dir = OPTS.openram_tech + lvs_name + "_lvs_lib/"
         except ImportError:
             lvs_dir = OPTS.openram_tech + "lvs_lib/"
@@ -338,19 +339,21 @@ class spice():
                 return
 
             # write out the first spice line (the subcircuit)
-            sp.write("\n.SUBCKT {0} {1}\n".format(self.cell_name,
-                                                  " ".join(self.pins)))
+            wrapped_pins = "\n+ ".join(tr.wrap(" ".join(self.pins)))
+            sp.write("\n.SUBCKT {0}\n+ {1}\n".format(self.cell_name,
+                                                     wrapped_pins))
 
             # write a PININFO line
-            pin_info = "*.PININFO"
-            for pin in self.pins:
-                if self.pin_type[pin] == "INPUT":
-                    pin_info += " {0}:I".format(pin)
-                elif self.pin_type[pin] == "OUTPUT":
-                    pin_info += " {0}:O".format(pin)
-                else:
-                    pin_info += " {0}:B".format(pin)
-            sp.write(pin_info + "\n")
+            if False:
+                pin_info = "*.PININFO"
+                for pin in self.pins:
+                    if self.pin_type[pin] == "INPUT":
+                        pin_info += " {0}:I".format(pin)
+                    elif self.pin_type[pin] == "OUTPUT":
+                        pin_info += " {0}:O".format(pin)
+                    else:
+                        pin_info += " {0}:B".format(pin)
+                sp.write(pin_info + "\n")
 
             # Also write pins as comments
             for pin in self.pins:
@@ -391,9 +394,11 @@ class spice():
                                                                    " ".join(self.conns[i])))
                     sp.write("\n")
                 else:
-                    sp.write("X{0} {1} {2}\n".format(self.insts[i].name,
-                                                     " ".join(self.conns[i]),
-                                                     self.insts[i].mod.cell_name))
+                    wrapped_connections = "\n+ ".join(tr.wrap(" ".join(self.conns[i])))
+
+                    sp.write("X{0}\n+ {1}\n+ {2}\n".format(self.insts[i].name,
+                                                           wrapped_connections,
+                                                           self.insts[i].mod.cell_name))
 
             sp.write(".ENDS {0}\n".format(self.cell_name))
 
@@ -409,6 +414,7 @@ class spice():
 
             sp.write("\n")
 
+
     def sp_write(self, spname, lvs=False, trim=False):
         """Writes the spice to files"""
         debug.info(3, "Writing to {0}".format(spname))

compiler/base/lef.py

@@ -1,17 +1,17 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from base import vector
-from base import pin_layout
-from tech import layer_names
 import os
 import shutil
-from globals import OPTS
+from openram import debug
+from openram.base import vector
+from openram.base import pin_layout
+from openram.tech import layer_names
+from openram import OPTS
 
 
 class lef:
@@ -64,7 +64,7 @@ class lef:
         f.write('puts "Finished writing LEF cell {}"\n'.format(self.name))
         f.close()
         os.system("chmod u+x {}".format(run_file))
-        from run_script import run_script
+        from openram.verify.run_script import run_script
         (outfile, errfile, resultsfile) = run_script(self.name, "lef")
 
     def lef_write(self, lef_name):

compiler/base/logical_effort.py

@@ -1,12 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import parameter
+from openram import debug
+from openram.tech import parameter
+
 
 class logical_effort():
     """

compiler/base/pin_layout.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import GDS, drc
-from .vector import vector
-from tech import layer, layer_indices
 import math
+from openram import debug
+from openram.tech import GDS, drc
+from openram.tech import layer, layer_indices
+from .vector import vector
 
 
 class pin_layout:
@@ -48,8 +48,8 @@ class pin_layout:
 
             else:
                 try:
-                    from tech import layer_override
-                    from tech import layer_override_name
+                    from openram.tech import layer_override
+                    from openram.tech import layer_override_name
                     if layer_override[name]:
                        self.lpp = layer_override[name]
                        self.layer = "pwellp"
@@ -406,15 +406,15 @@ class pin_layout:
         # Try to use a global pin purpose if it exists,
         # otherwise, use the regular purpose
         try:
-            from tech import pin_purpose as global_pin_purpose
+            from openram.tech import pin_purpose as global_pin_purpose
             pin_purpose = global_pin_purpose
         except ImportError:
             pass
 
         try:
-            from tech import label_purpose
+            from openram.tech import label_purpose
             try:
-                from tech import layer_override_purpose
+                from openram.tech import layer_override_purpose
                 if pin_layer_num in layer_override_purpose:
                     layer_num = layer_override_purpose[pin_layer_num][0]
                     label_purpose = layer_override_purpose[pin_layer_num][1]

compiler/base/power_data.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/route.py

@@ -1,17 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from itertools import tee
+from openram import debug
+from openram.sram_factory import factory
+from openram.tech import drc
 from .design import design
 from .vector import vector
 from .vector3d import vector3d
-from tech import drc
-from itertools import tee
-from sram_factory import factory
+
 
 class route(design):
     """

compiler/base/timing_graph.py

@@ -1,7 +1,11 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 import copy
 from collections import defaultdict
-import debug
-import json
+from openram import debug
 
 
 class timing_graph():
@@ -140,35 +144,6 @@ class timing_graph():
 
         return [self.edge_mods[(path[i], path[i+1])] for i in range(len(path)-1)]
 
-    def write(self, filename):
-        """
-        Export graph to a JSON file
-        """
-        # TODO: Find a proper way to store edge_mods values
-        with open(filename, 'w') as f:
-            f.write(
-                json.dumps(
-                    {
-                        'graph':
-                            {key: list(val) for key, val in self.graph.items()},
-                        'edge_mods':
-                            {
-                                ', '.join(key): str(value)
-                                for key, value in self.edge_mods.items()
-                            }
-                    }
-                )
-            )
-
-    def read(self, filename):
-        """
-        Read graph from JSON file
-        """
-        with open(filename, 'r') as f:
-            d = json.loads(f.read())
-            self.graph = {key: set(value) for key, value in d['graph'].items()}
-            self.edge_mods = {tuple(key.split(', ')): value for key, value in d['edge_mods'].items()}
-
     def __str__(self):
         """ override print function output """
 

compiler/base/utils.py

@@ -1,24 +1,22 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
-
+#
 import os
 import math
-
-from gdsMill import gdsMill
-import tech
-import globals
-import debug
+from openram import debug
+from openram import tech
+from openram.gdsMill import gdsMill
+from openram import OPTS
 from .vector import vector
 from .pin_layout import pin_layout
 try:
-    from tech import special_purposes
+    from openram.tech import special_purposes
 except ImportError:
     special_purposes = {}
-OPTS = globals.OPTS
 
 
 def ceil(decimal):
@@ -159,7 +157,7 @@ def get_gds_pins(pin_names, name, gds_filename, units):
                     # may have must-connect pins
                     if isinstance(lpp[1], list):
                         try:
-                            from tech import layer_override
+                            from openram.tech import layer_override
                             if layer_override[pin_name]:
                                 lpp = layer_override[pin_name.textString]
                         except:

compiler/base/vector.py

@@ -1,13 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
 import math
-import tech
+from openram import tech
 
 
 class vector():

compiler/base/vector3d.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/base/verilog.py

@@ -1,12 +1,12 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import math
-from tech import spice
+from openram.tech import spice
 
 
 class verilog:

compiler/base/wire.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc
+from openram.tech import drc
+from openram.sram_factory import factory
 from .wire_path import wire_path
-from sram_factory import factory
 
 
 class wire(wire_path):
@@ -71,7 +71,7 @@ class wire(wire_path):
 
         # This is here for the unit tests which may not have
         # initialized the static parts of the layout class yet.
-        from base import layout
+        from openram.base import layout
         layout("fake", "fake")
 
         (layer1, via, layer2) = layer_stack

compiler/base/wire_path.py

@@ -1,15 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .vector import vector
-from .utils import snap_to_grid
+from openram.tech import drc
+from openram.tech import layer as techlayer
 from .design import design
-from tech import drc
-from tech import layer as techlayer
+from .utils import snap_to_grid
+from .vector import vector
+
 
 def create_rectilinear_route(my_list):
     """ Add intermediate nodes if it isn't rectilinear. Also skip

compiler/base/wire_spice_model.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -16,14 +16,14 @@ class wire_spice_model():
         self.wire_r = self.cal_wire_r(wire_length, wire_width) # r in each segment
 
     def cal_wire_c(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         # Convert the F/um^2 to fF/um^2 then multiple by width and length
         total_c = (spice["wire_unit_c"]*1e12) * wire_length * wire_width
         wire_c = total_c / self.lump_num
         return wire_c
 
     def cal_wire_r(self, wire_length, wire_width):
-        from tech import spice
+        from openram.tech import spice
         total_r = spice["wire_unit_r"] * wire_length / wire_width
         wire_r = total_r / self.lump_num
         return wire_r

compiler/characterizer/__init__.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import os
-import debug
-from globals import OPTS, find_exe, get_tool
+from openram import debug
+from openram import OPTS, find_exe, get_tool
 from .lib import *
 from .delay import *
 from .elmore import *
@@ -56,4 +56,3 @@ if not OPTS.analytical_delay:
 else:
     debug.info(1, "Analytical model enabled.")
 
-

compiler/characterizer/analytical_util.py

@@ -1,16 +1,16 @@
+# See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-import debug
-
+import os
 import csv
 import math
 import numpy as np
-import os
+from openram import debug
+
 
 process_transform = {'SS':0.0, 'TT': 0.5, 'FF':1.0}
 

compiler/characterizer/bit_polarity.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/cacti.py

@@ -1,17 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .simulation import simulation
-from globals import OPTS
-import debug
-import tech
-
 import math
+from openram import debug
+from openram import tech
+from openram import OPTS
+from .simulation import simulation
+
 
 class cacti(simulation):
     """

compiler/characterizer/charutils.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 import os
 import re
-import debug
-from globals import OPTS
+from openram import debug
+from openram import OPTS
 
 
 def relative_compare(value1, value2, error_tolerance=0.001):

compiler/characterizer/delay.py

@@ -1,20 +1,20 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import shutil
-import debug
-import tech
 import math
+import shutil
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
 from .sram_op import *
 from .bit_polarity import *
-from globals import OPTS
 from .simulation import simulation
 from .measurements import *
 from os import path

compiler/characterizer/elmore.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+from openram import debug
+from openram import OPTS
 from .simulation import simulation
-from globals import OPTS
-import debug
+
 
 class elmore(simulation):
     """

compiler/characterizer/fake_sram.py

@@ -1,4 +1,4 @@
-from modules import sram_config
+from openram.modules import sram_config
 from math import ceil
 import re
 

compiler/characterizer/fake_sram_v2.py

@@ -1,51 +0,0 @@
-# This is a temp file. Remove either this or the fake_sram.py
-
-from modules import sram
-import debug
-from globals import OPTS
-import os
-
-
-class fake_sram_v2(sram):
-
-    def create_netlist(self):
-        # Make sure spice file is here
-        debug.check(os.path.exists(self.sp_name), "Spice netlist in {} not found".format(self.sp_name))
-
-    def generate_pins(self):
-        self.pins = ['vdd', 'gnd']
-        self.pins.extend(['clk{}'.format(port) for port in range(
-            OPTS.num_rw_ports + OPTS.num_r_ports + OPTS.num_w_ports)])
-        for port in range(OPTS.num_rw_ports):
-            self.pins.extend(['din{0}[{1}]'.format(port, bit)
-                              for bit in range(self.num_cols)])
-            self.pins.extend(['dout{0}[{1}]'.format(port, bit)
-                              for bit in range(self.num_cols)])
-            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
-                              for bit in range(self.addr_size)])
-            #if self.num_wmasks != 0:
-            #    self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
-            #                      for bit in range(self.num_wmasks)])
-
-            self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
-
-        start_port = OPTS.num_rw_ports
-        for port in range(start_port, start_port + OPTS.num_r_ports):
-            self.pins.extend(['dout{0}[{1}]'.format(port, bit)
-                              for bit in range(self.num_cols)])
-            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
-                              for bit in range(self.addr_size)])
-
-            self.pins.extend(['csb{}'.format(port)])
-
-        start_port += OPTS.num_r_ports
-        for port in range(start_port, start_port + OPTS.num_w_ports):
-            self.pins.extend(['din{0}[{1}]'.format(port, bit)
-                              for bit in range(self.num_cols)])
-            self.pins.extend(['addr{0}[{1}]'.format(port, bit)
-                              for bit in range(self.addr_size)])
-            if self.num_wmasks != 0:
-                self.pins.extend(['wmask{0}[{1}]'.format(port, bit)
-                                  for bit in range(self.num_wmasks)])
-
-            self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])

compiler/characterizer/functional.py

@@ -1,18 +1,18 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import collections
-import debug
-import random
 import math
+import random
+import collections
 from numpy import binary_repr
+from openram import debug
+from openram import OPTS
 from .stimuli import *
 from .charutils import *
-from globals import OPTS
 from .simulation import simulation
 from .measurements import voltage_at_measure
 

compiler/characterizer/lib.py

@@ -1,21 +1,21 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os,sys,re
+import os, sys, re
 import time
-import debug
 import datetime
+import numpy as np
+from openram import debug
+from openram import tech
+from openram.tech import spice
+from openram import OPTS
 from .setup_hold import *
 from .delay import *
 from .charutils import *
-import tech
-import numpy as np
-from globals import OPTS
-from tech import spice
 
 
 class lib:

compiler/characterizer/linear_regression.py

@@ -1,17 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
 from sklearn.linear_model import Ridge
-from globals import OPTS
-import debug
-
 from sklearn.linear_model import LinearRegression
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class linear_regression(regression_model):

compiler/characterizer/measurements.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from tech import drc, parameter, spice
 from abc import ABC, abstractmethod
+from openram import debug
+from openram.tech import drc, parameter, spice
 from .stimuli import *
 from .charutils import *
 

compiler/characterizer/model_check.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import tech
+from openram import debug
+from openram import tech
+from openram import OPTS
 from .stimuli import *
 from .trim_spice import *
 from .charutils import *
-from globals import OPTS
 from .delay import delay
 from .measurements import *
 

compiler/characterizer/neural_network.py

@@ -1,15 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
-from .regression_model import regression_model
-from globals import OPTS
-import debug
 from sklearn.neural_network import MLPRegressor
+from openram import debug
+from openram import OPTS
+from .regression_model import regression_model
 
 
 class neural_network(regression_model):

compiler/characterizer/regression_model.py

@@ -1,17 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-
+import math
+from openram import debug
+from openram import OPTS
 from .analytical_util import *
 from .simulation import simulation
-from globals import OPTS
-import debug
 
-import math
 
 relative_data_path = "sim_data"
 data_file = "sim_data.csv"

compiler/characterizer/setup_hold.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import tech
+from openram import debug
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 from .stimuli import *
-import debug
 from .charutils import *
-from globals import OPTS
-from sram_factory import factory
 
 
 class setup_hold():

compiler/characterizer/simulation.py

@@ -1,16 +1,16 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
 import math
-import tech
-from globals import OPTS
-from sram_factory import factory
-from base import timing_graph
+from openram import debug
+from openram.base import timing_graph
+from openram.sram_factory import factory
+from openram import tech
+from openram import OPTS
 
 
 class simulation():

compiler/characterizer/sram_op.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/characterizer/stimuli.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -11,12 +11,12 @@ various functions that can be be used to generate stimulus for other
 simulations as well.
 """
 
-import tech
-import debug
-import subprocess
 import os
+import subprocess
 import numpy as np
-from globals import OPTS
+from openram import debug
+from openram import tech
+from openram import OPTS
 
 
 class stimuli():

compiler/characterizer/trim_spice.py

@@ -1,13 +1,13 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-from math import log,ceil
 import re
+from math import log, ceil
+from openram import debug
 
 
 class trim_spice():

compiler/datasheet/__init__.py

@@ -1 +1,6 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 from .datasheet_gen import datasheet_gen

compiler/datasheet/add_db.py

@@ -1,14 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from pathlib import Path
-import glob
-import os
 import sys
+import os
+import glob
+from pathlib import Path
+
 
 # This is the path to the directory you would like to search
 # This directory is searched recursively for .html files

compiler/datasheet/datasheet.py

@@ -1,14 +1,14 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from .table_gen import *
 import os
 import base64
-from globals import OPTS
+from openram import OPTS
+from .table_gen import *
 
 
 class datasheet():

compiler/datasheet/datasheet_gen.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -15,10 +15,10 @@ a web friendly html datasheet.
 # Improve css
 
 
-from globals import OPTS
 import os
 import math
 import csv
+from openram import OPTS
 from .datasheet import datasheet
 from .table_gen import table_gen
 

compiler/datasheet/table_gen.py

@@ -1,12 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 
-
 class table_gen:
     """small library of functions to generate the html tables"""
 

compiler/debug.py

@@ -1,15 +1,15 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import os
-import inspect
-import globals
 import sys
+import os
 import pdb
+import inspect
+from openram import globals
 
 # the debug levels:
 # 0 = minimum output (default)
@@ -96,7 +96,7 @@ log.create_file = True
 
 
 def info(lev, str):
-    from globals import OPTS
+    from openram.globals import OPTS
     # 99 is a special never print level
     if lev == 99:
         return
@@ -114,7 +114,7 @@ def info(lev, str):
 
 
 def archive():
-    from globals import OPTS
+    from openram.globals import OPTS
     try:
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
     except:

compiler/drc/__init__.py

@@ -1,3 +1,8 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 from .custom_cell_properties import *
 from .custom_layer_properties import *
 from .design_rules import *

compiler/drc/custom_cell_properties.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2020 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/drc/custom_layer_properties.py

@@ -1,12 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2020 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 
-
 class _bank:
     def __init__(self, stack, pitch):
         # bank

compiler/drc/design_rules.py

@@ -1,11 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 from .drc_value import *
 from .drc_lut import *
 

compiler/drc/drc_lut.py

@@ -1,11 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
+from openram import debug
 
 
 class drc_lut():

compiler/drc/drc_value.py

@@ -1,12 +1,11 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
 
-
 class drc_value():
     """
     A single DRC value.

compiler/drc/module_type.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/gdsMill/gdsMill/pdfLayout.py

@@ -1,8 +1,8 @@
-import pyx
 import math
-from numpy import matrix
-from gdsPrimitives import *
 import random
+from numpy import matrix
+from openram.gdsMill import pyx
+from .gdsPrimitives import *
 
 class pdfLayout:
     """Class representing a view for a layout as a PDF"""

compiler/gdsMill/gdsMill/vlsiLayout.py

@@ -1,8 +1,8 @@
-from .gdsPrimitives import *
+import math
 from datetime import *
 import numpy as np
-import math
-import debug
+from openram import debug
+from .gdsPrimitives import *
 
 
 class VlsiLayout:
@@ -774,7 +774,7 @@ class VlsiLayout:
             else:
                 label_text = label.textString
             try:
-                from tech import layer_override
+                from openram.tech import layer_override
                 if layer_override[label_text]:
                     shapes = self.getAllShapes((layer_override[label_text][0], None))
                     if not shapes:

compiler/gen_stimulus.py

@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.

compiler/globals.py

@@ -1,6 +1,6 @@
 # See LICENSE for licensing information.
 #
-# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# Copyright (c) 2016-2022 Regents of the University of California and The Board
 # of Regents for the Oklahoma Agricultural and Mechanical College
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
@@ -9,17 +9,17 @@
 This is called globals.py, but it actually parses all the arguments
 and performs the global OpenRAM setup as well.
 """
+import sys
 import os
-import debug
+import re
 import shutil
 import optparse
-import options
-import sys
-import re
 import copy
 import importlib
 import getpass
 import subprocess
+from openram import debug
+from openram import options
 
 
 VERSION = "1.2.0"
@@ -185,7 +185,7 @@ def check_versions():
         OPTS.coverage = 0
 
 
-def init_openram(config_file, is_unit_test=True):
+def init_openram(config_file, is_unit_test=False):
     """ Initialize the technology, paths, simulators, etc. """
 
     check_versions()
@@ -202,7 +202,7 @@ def init_openram(config_file, is_unit_test=True):
 
     init_paths()
 
-    from sram_factory import factory
+    from openram.sram_factory import factory
     factory.reset()
 
     global OPTS
@@ -222,8 +222,8 @@ def init_openram(config_file, is_unit_test=True):
     setup_bitcell()
 
     # Import these to find the executables for checkpointing
-    import characterizer
-    import verify
+    from openram import characterizer
+    from openram import verify
     # Make a checkpoint of the options so we can restore
     # after each unit test
     if not CHECKPOINT_OPTS:
@@ -249,7 +249,7 @@ def setup_bitcell():
 
     # See if bitcell exists
     try:
-        c = importlib.import_module("modules." + OPTS.bitcell)
+        c = importlib.import_module("openram.modules." + OPTS.bitcell)
         mod = getattr(c, OPTS.bitcell)
     except ImportError:
         # Use the pbitcell if we couldn't find a custom bitcell
@@ -294,7 +294,7 @@ def get_tool(tool_type, preferences, default_name=None):
             return(None, "")
 
 
-def read_config(config_file, is_unit_test=True):
+def read_config(config_file, is_unit_test=False):
     """
     Read the configuration file that defines a few parameters. The
     config file is just a Python file that defines some config
@@ -385,7 +385,7 @@ def end_openram():
     cleanup_paths()
 
     if OPTS.check_lvsdrc:
-        import verify
+        from openram import verify
         verify.print_drc_stats()
         verify.print_lvs_stats()
         verify.print_pex_stats()
@@ -429,24 +429,9 @@ def setup_paths():
 
     global OPTS
 
-    # If $OPENRAM_HOME is defined, use that path for the source code.
-    # Otherwise, use the openram package.
-    try:
-        OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-    except:
-        import openram
-        OPENRAM_HOME = os.path.dirname(openram.__file__) + "/compiler"
-        # Add this directory to os.environ here
-        os.environ["OPENRAM_HOME"] = OPENRAM_HOME
-
-    debug.check(os.path.isdir(OPENRAM_HOME),
-                "$OPENRAM_HOME does not exist: {0}".format(OPENRAM_HOME))
+    from openram import OPENRAM_HOME
     debug.info(1, "OpenRAM source code found in {}".format(OPENRAM_HOME))
 
-    if OPENRAM_HOME not in sys.path:
-        sys.path.insert(0, OPENRAM_HOME)
-        debug.info(2, "Adding source code to PYTHONPATH.")
-
     # Use a unique temp subdirectory if multithreaded
     if OPTS.num_threads > 1 or OPTS.openram_temp == "/tmp":
 
@@ -515,7 +500,7 @@ def init_paths():
 def set_default_corner():
     """ Set the default corner. """
 
-    import tech
+    from openram import tech
     # Set some default options now based on the technology...
     if (OPTS.process_corners == ""):
         if OPTS.nominal_corner_only:
@@ -548,8 +533,7 @@ def import_tech():
     """ Dynamically adds the tech directory to the path and imports it. """
     global OPTS
 
-    debug.info(2,
-               "Importing technology: " + OPTS.tech_name)
+    debug.info(2, "Importing technology: " + OPTS.tech_name)
 
     OPENRAM_TECH = ""
 
@@ -591,18 +575,23 @@ def import_tech():
 
     OPTS.openram_tech = os.path.dirname(tech_mod.__file__) + "/"
 
-    # Prepend the tech directory so it is sourced FIRST
+    # Append tech_path to openram.__path__ to import it from openram
     tech_path = OPTS.openram_tech
-    sys.path.insert(0, tech_path)
+    openram.__path__.append(tech_path)
     try:
-        import tech
+        from openram import tech
     except ImportError:
         debug.error("Could not load tech module.", -1)
 
-    # Prepend custom modules of the technology to the path, if they exist
-    custom_mod_path = os.path.join(tech_path, "modules/")
+    # Remove OPENRAM_TECH from sys.path because we should be done with those
+    for tech_path in OPENRAM_TECH.split(":"):
+        sys.path.remove(tech_path)
+
+    # Add the custom modules to "tech"
+    custom_mod_path = os.path.join(tech_path, "custom/")
     if os.path.exists(custom_mod_path):
-        sys.path.insert(0, custom_mod_path)
+        from openram import tech
+        tech.__path__.append(custom_mod_path)
 
 
 def print_time(name, now_time, last_time=None, indentation=2):

compiler/model_configs/shared_config.py

@@ -1 +1,6 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 model_name = "cacti"

compiler/model_configs/sram_10b_64w_4wpr_21las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 10
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_128b_1024_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 128
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_12b_128w_4wpr_38las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 12
 num_words = 128
 words_per_row = 4

compiler/model_configs/sram_12b_16w_1wpr_1las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 12
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_12b_256w_16wpr_186las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_12b_256w_8wpr_17las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 12
 num_words = 256
 words_per_row = 8

compiler/model_configs/sram_14b_32w_2wpr_23las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 14
 num_words = 32
 words_per_row = 2

compiler/model_configs/sram_15b_512w_8wpr_85las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 15
 num_words = 512
 words_per_row = 8

compiler/model_configs/sram_16b_1024w_16wpr_40las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 16
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_17b_1024w_16wpr_86las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 17
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_17b_256w_16wpr_49las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 17
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_18b_128w_2wpr_7las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 18
 num_words = 128
 words_per_row = 2

compiler/model_configs/sram_18b_32w_1wpr_18las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 18
 num_words = 32
 words_per_row = 1

compiler/model_configs/sram_21b_1024w_4wpr_54las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 21
 num_words = 1024
 words_per_row = 4

compiler/model_configs/sram_22b_512w_16wpr_249las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 22
 num_words = 512
 words_per_row = 16

compiler/model_configs/sram_23b_1024w_16wpr_118las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 23
 num_words = 1024
 words_per_row = 16

compiler/model_configs/sram_26b_64w_4wpr_23las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 26
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_27b_1024w_4wpr_89las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 27
 num_words = 1024
 words_per_row = 4

compiler/model_configs/sram_27b_256w_8wpr_191las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 27
 num_words = 256
 words_per_row = 8

compiler/model_configs/sram_27b_512w_4wpr_60las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 27
 num_words = 512
 words_per_row = 4

compiler/model_configs/sram_32b_1024_1rw.py

@@ -1,3 +1,8 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
 from shared_config import *
 word_size = 32
 num_words = 1024
@@ -5,4 +10,4 @@ num_words = 1024
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_2048_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 32
 num_words = 2048
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_256_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 32
 num_words = 256
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_32b_32w_1wpr_31las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 32
 num_words = 32
 words_per_row = 1

compiler/model_configs/sram_32b_512_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 32
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_4b_16w_1wpr_4las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 4
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_4b_32w_2wpr_5las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 4
 num_words = 32
 words_per_row = 2

compiler/model_configs/sram_4b_64w_4wpr_14las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 4
 num_words = 64
 words_per_row = 4

compiler/model_configs/sram_5b_256w_16wpr_75las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 5
 num_words = 256
 words_per_row = 16

compiler/model_configs/sram_64b_1024_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 64
 num_words = 1024
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_64b_512_1rw.py

@@ -1,8 +1,13 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 64
 num_words = 512
 
 output_extended_config = True
 output_datasheet_info = True
 netlist_only = True
-nominal_corner_only = True
+nominal_corner_only = True

compiler/model_configs/sram_6b_16w_1wpr_1las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 6
 num_words = 16
 words_per_row = 1

compiler/model_configs/sram_7b_256w_4wpr_25las_1rw.py

@@ -1,4 +1,9 @@
-from shared_config import *
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2022 Regents of the University of California, Santa Cruz
+# All rights reserved.
+#
+from .shared_config import *
 word_size = 7
 num_words = 256
 words_per_row = 4