mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed issue with sen measurement not being added
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@ -186,7 +186,7 @@ class delay(simulation):
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self.sen_meas.meta_str = sram_op.READ_ZERO
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self.sen_meas.meta_add_delay = True
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return self.dout_volt_meas
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return self.dout_volt_meas + [self.sen_meas]
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def create_read_bit_measures(self):
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""" Adds bit measurements for read0 and read1 cycles """
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