mirror of https://github.com/VLSIDA/OpenRAM.git
Fix 1w/1r example
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@ -1,9 +1,9 @@
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word_size = 2
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num_words = 16
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num_rw_ports = 1
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num_rw_ports = 0
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num_r_ports = 1
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num_w_ports = 0
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num_w_ports = 1
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tech_name = "scn4m_subm"
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nominal_corners_only = False
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