mirror of https://github.com/VLSIDA/OpenRAM.git
Changed multiport characterization warning to better fit
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@ -1350,7 +1350,7 @@ class delay(simulation):
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Return the analytical model results for the SRAM.
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"""
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if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
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debug.warning("Analytical characterization results are not supported for multiport.")
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debug.warning("Analytical characterization for multiple read ports may be inaccurate.")
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# Probe set to 0th bit, does not matter for analytical delay.
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self.set_probe('0'*self.addr_size, 0)
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