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update to new metal stack names

This commit is contained in:
jcirimel 2020-07-31 05:27:19 -07:00
parent 1d9296ceb1
commit 3221b4ec57
3 changed files with 14 additions and 14 deletions
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4
compiler/bitcells/bitcell.py
View File

@ -33,7 +33,7 @@ class bitcell(bitcell_base.bitcell_base):
props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Qbar']
storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_6t",
GDS["unit"],
@ -51,7 +51,7 @@ class bitcell(bitcell_base.bitcell_base):
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets)
debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
# debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
def get_all_wl_names(self):
""" Creates a list of all wordline pin names """

6
compiler/bitcells/bitcell_base.py
View File

@ -89,7 +89,7 @@ class bitcell_base(design.design):
if OPTS.bitcell is not "pbitcell":
self.storage_net_offsets = []
for i in range(len(self.get_storage_net_names())):
for text in self.gds.getTexts(layer["metal1"]):
for text in self.gds.getTexts(layer["m1"]):
if self.storage_nets[i] == text.textString.rstrip('\x00'):
self.storage_net_offsets.append(text.coordinates[0])
@ -111,7 +111,7 @@ class bitcell_base(design.design):
self.br_offsets = []
for i in range(len(bl_names)):
for text in self.gds.getTexts(layer["metal2"]):
for text in self.gds.getTexts(layer["m2"]):
if not bl_names[i] in found_bl:
if bl_names[i] == text.textString.rstrip('\x00'):
self.bl_offsets.append(text.coordinates[0])
@ -120,7 +120,7 @@ class bitcell_base(design.design):
continue
for i in range(len(br_names)):
for text in self.gds.getTexts(layer["metal2"]):
for text in self.gds.getTexts(layer["m2"]):
if not br_names[i] in found_br:
if br_names[i] == text.textString.rstrip('\x00'):
self.br_offsets.append(text.coordinates[0])

18
compiler/bitcells/pbitcell.py
View File

@ -401,16 +401,16 @@ class pbitcell(bitcell_base.bitcell_base):
gate_offset_left = vector(self.inverter_nmos_left.get_pin("G").rc().x,
contact_offset_right.y)
self.add_path("poly", [contact_offset_right, gate_offset_left])
if OPTS.use_pex:
# add labels to cross couple inverter for extracted simulation
contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \
+ 0.5 * contact.poly.height,
self.cross_couple_upper_ypos)
contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \
- 0.5*contact.poly.height,
self.cross_couple_lower_ypos)
self.add_pex_labels(contact_offset_left_output, contact_offset_right_output)
contact_offset_left_output = vector(self.inverter_nmos_left.get_pin("D").rc().x \
+ 0.5 * contact.poly.height,
self.cross_couple_upper_ypos)
contact_offset_right_output = vector(self.inverter_nmos_right.get_pin("S").lc().x \
- 0.5*contact.poly.height,
self.cross_couple_lower_ypos)
self.add_pex_labels(contact_offset_left_output, contact_offset_right_output)
def route_rails(self):
""" Adds gnd and vdd rails and connects them to the inverters """