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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

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mrg 2020-07-30 08:44:25 -07:00
parent 68387ec525 c6f2edc20d
commit a663d903c5
1 changed files with 1 additions and 1 deletions
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2
compiler/characterizer/delay.py
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@ -1350,7 +1350,7 @@ class delay(simulation):
Return the analytical model results for the SRAM.
"""
if OPTS.num_rw_ports > 1 or OPTS.num_w_ports > 0 and OPTS.num_r_ports > 0:
debug.warning("Analytical characterization for multiple read ports may be inaccurate.")
debug.warning("In analytical mode, all ports have the timing of the first read port.")
# Probe set to 0th bit, does not matter for analytical delay.
self.set_probe('0'*self.addr_size, 0)