mirror of https://github.com/VLSIDA/OpenRAM.git
Merge remote-tracking branch 'private/dev' into dev
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commit
64d61f4d56
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@ -160,7 +160,10 @@ class sram_1bank(sram_base):
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port = 0
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# Add the col address flops below the bank to the right of the control logic
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x_offset = self.control_logic_insts[port].rx() + self.dff.width
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y_offset = - self.data_bus_size[port] - self.dff.height
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# Place it a data bus below the x-axis, but at least as low as the control logic to not block
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# the control logic signals
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y_offset = min(-self.data_bus_size[port] - self.dff.height,
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self.control_logic_insts[port].by())
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if self.col_addr_dff:
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self.col_addr_pos[port] = vector(x_offset,
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y_offset)
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@ -201,7 +204,10 @@ class sram_1bank(sram_base):
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# Add the col address flops below the bank to the right of the control logic
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x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width
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y_offset = self.bank.height + self.data_bus_size[port] + self.dff.height
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# Place it a data bus below the x-axis, but at least as high as the control logic to not block
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# the control logic signals
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y_offset = max(self.bank.height + self.data_bus_size[port] + self.dff.height,
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self.control_logic_insts[port].uy() - self.dff.height)
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if self.col_addr_dff:
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self.col_addr_pos[port] = vector(x_offset,
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y_offset)
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