mirror of https://github.com/VLSIDA/OpenRAM.git
DRC/LVS and errors fixes.
Only enact pdb if assert fails in debug.error. Only run drc/lvs one time in parse_info by saving result. Cleanup drc/lvs output.
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372a8a728e
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@ -7,7 +7,6 @@
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#
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import hierarchy_layout
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import hierarchy_spice
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import verify
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import debug
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import os
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from globals import OPTS
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@ -55,6 +54,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
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def DRC_LVS(self, final_verification=False, force_check=False):
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"""Checks both DRC and LVS for a module"""
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import verify
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# No layout to check
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if OPTS.netlist_only:
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@ -94,6 +94,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
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def DRC(self, final_verification=False):
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"""Checks DRC for a module"""
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import verify
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# Unit tests will check themselves.
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# Do not run if disabled in options.
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@ -117,6 +119,8 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
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def LVS(self, final_verification=False):
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"""Checks LVS for a module"""
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import verify
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# Unit tests will check themselves.
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# Do not run if disabled in options.
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@ -657,8 +657,12 @@ class lib:
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))
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# information of checks
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(drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True)
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datasheet.write("{0},{1},".format(drc_errors, lvs_errors))
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# run it only the first time
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try:
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datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors))
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except AttributeError:
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(self.drc_errors, self.lvs_errors) = self.sram.DRC_LVS(final_verification=True)
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datasheet.write("{0},{1},".format(self.drc_errors, self.lvs_errors))
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# write area
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datasheet.write(str(self.sram.width * self.sram.height) + ',')
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@ -40,7 +40,7 @@ def error(str, return_value=0):
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log("ERROR: file {0}: line {1}: {2}\n".format(
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os.path.basename(filename), line_number, str))
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if globals.OPTS.debug_level > 0:
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if globals.OPTS.debug_level > 0 and return_value != 0:
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import pdb
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pdb.set_trace()
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assert return_value == 0
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@ -219,16 +219,14 @@ def run_drc(cell_name, gds_name, extract=False, final_verification=False):
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errors = int(re.split(r'\W+', results[2])[5])
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# always display this summary
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if errors > 0:
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debug.error("{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name,
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result_str = "{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name,
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geometries,
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rulechecks,
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errors))
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errors)
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if errors > 0:
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debug.warning(result_str)
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else:
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debug.info(1, "{0}\tGeometries: {1}\tChecks: {2}\tErrors: {3}".format(cell_name,
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geometries,
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rulechecks,
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errors))
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debug.info(1, result_str)
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return errors
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@ -307,16 +305,15 @@ def run_lvs(cell_name, gds_name, sp_name, final_verification=False):
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out_errors = len(stdouterrors)
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total_errors = summary_errors + out_errors + ext_errors
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if total_errors > 0:
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debug.error("{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name,
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# always display this summary
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result_str = "{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name,
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summary_errors,
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out_errors,
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ext_errors))
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ext_errors)
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if total_errors > 0:
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debug.warning(result_str)
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else:
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debug.info(1, "{0}\tSummary: {1}\tOutput: {2}\tExtraction: {3}".format(cell_name,
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summary_errors,
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out_errors,
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ext_errors))
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debug.info(1, result_str)
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return total_errors
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@ -200,13 +200,14 @@ def run_drc(cell_name, gds_name, extract=True, final_verification=False):
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# always display this summary
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result_str = "DRC Errors {0}\t{1}".format(cell_name, errors)
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if errors > 0:
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for line in results:
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if "error tiles" in line:
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debug.info(1,line.rstrip("\n"))
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debug.error("DRC Errors {0}\t{1}".format(cell_name, errors))
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debug.warning(result_str)
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else:
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debug.info(1, "DRC Errors {0}\t{1}".format(cell_name, errors))
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debug.info(1, result_str)
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return errors
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