mirror of https://github.com/VLSIDA/OpenRAM.git
Modifications for min area metal.
Made add_via_stack_center iterative instead of recursive. Removed add_via_stack (non-center) since it isn't used. Add min area metal during iterative via insertion.
This commit is contained in:
mrg
parent
011ac2fc05
commit
c1fedda575
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@ -13,6 +13,7 @@ from tech import drc, GDS
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from tech import layer as techlayer
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from tech import layer_indices
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from tech import layer_stacks
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from tech import preferred_directions
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import os
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from globals import OPTS
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from vector import vector
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@ -521,7 +522,6 @@ class layout():
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def get_preferred_direction(self, layer):
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""" Return the preferred routing directions """
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from tech import preferred_directions
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return preferred_directions[layer]
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def add_via(self, layers, offset, size=[1, 1], directions=None, implant_type=None, well_type=None):
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@ -567,24 +567,6 @@ class layout():
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self.connect_inst([])
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return inst
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def add_via_stack(self, offset, from_layer, to_layer,
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directions=None,
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size=[1, 1],
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implant_type=None,
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well_type=None):
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"""
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Punch a stack of vias from a start layer to a target layer.
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"""
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return self.__add_via_stack_internal(offset=offset,
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directions=directions,
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from_layer=from_layer,
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to_layer=to_layer,
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via_func=self.add_via,
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last_via=None,
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size=size,
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implant_type=implant_type,
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well_type=well_type)
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def add_via_stack_center(self,
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offset,
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from_layer,
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@ -594,24 +576,7 @@ class layout():
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implant_type=None,
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well_type=None):
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"""
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Punch a stack of vias from a start layer to a target layer by the center
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coordinate accounting for mirroring and rotation.
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"""
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return self.__add_via_stack_internal(offset=offset,
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directions=directions,
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from_layer=from_layer,
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to_layer=to_layer,
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via_func=self.add_via_center,
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last_via=None,
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size=size,
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implant_type=implant_type,
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well_type=well_type)
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def __add_via_stack_internal(self, offset, directions, from_layer, to_layer,
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via_func, last_via, size, implant_type=None, well_type=None):
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"""
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Punch a stack of vias from a start layer to a target layer. Here we
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figure out whether to punch it up or down the stack.
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Punch a stack of vias from a start layer to a target layer by the center.
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"""
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if from_layer == to_layer:
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@ -619,38 +584,65 @@ class layout():
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# a metal enclosure. This helps with center-line path routing.
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self.add_rect_center(layer=from_layer,
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offset=offset)
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return last_via
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return None
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from_id = layer_indices[from_layer]
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to_id = layer_indices[to_layer]
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via = None
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cur_layer = from_layer
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while cur_layer != to_layer:
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from_id = layer_indices[cur_layer]
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to_id = layer_indices[to_layer]
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if from_id < to_id: # grow the stack up
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search_id = 0
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next_id = 2
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else: # grow the stack down
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search_id = 2
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next_id = 0
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if from_id < to_id: # grow the stack up
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search_id = 0
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next_id = 2
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else: # grow the stack down
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search_id = 2
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next_id = 0
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curr_stack = next(filter(lambda stack: stack[search_id] == from_layer, layer_stacks), None)
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if curr_stack is None:
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raise ValueError("Cannot create via from '{0}' to '{1}'."
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"Layer '{0}' not defined".format(from_layer, to_layer))
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curr_stack = next(filter(lambda stack: stack[search_id] == cur_layer, layer_stacks), None)
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via = self.add_via_center(layers=curr_stack,
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size=size,
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offset=offset,
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directions=directions,
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implant_type=implant_type,
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well_type=well_type)
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if cur_layer != from_layer:
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self.add_min_area_rect_center(cur_layer,
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offset,
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via.mod.first_layer_width,
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via.mod.first_layer_height)
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cur_layer = curr_stack[next_id]
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via = via_func(layers=curr_stack,
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size=size,
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offset=offset,
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directions=directions,
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implant_type=implant_type,
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well_type=well_type)
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via = self.__add_via_stack_internal(offset=offset,
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directions=directions,
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from_layer=curr_stack[next_id],
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to_layer=to_layer,
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via_func=via_func,
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last_via=via,
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size=size)
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return via
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def add_min_area_rect_center(self,
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layer,
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offset,
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width=None,
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height=None):
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"""
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Add a minimum area retcangle at the given point.
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Either width or height should be fixed.
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"""
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min_area = drc("minarea_{}".format(layer))
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if min_area == 0:
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return
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min_width = drc("minwidth_{}".format(layer))
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if preferred_directions[layer] == "V":
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height = max(min_area / width, min_width)
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else:
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width = max(min_area / height, min_width)
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self.add_rect_center(layer=layer,
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offset=offset,
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width=width,
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height=height)
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def add_ptx(self, offset, mirror="R0", rotate=0, width=1, mults=1, tx_type="nmos"):
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"""Adds a ptx module to the design."""
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@ -1181,12 +1173,8 @@ class layout():
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self.add_path(layer,
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[pin_loc, peri_pin_loc])
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self.add_via_stack_center(from_layer=layer,
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to_layer="m4",
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offset=peri_pin_loc)
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self.add_layout_pin_rect_center(text=name,
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layer="m4",
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layer=layer,
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offset=peri_pin_loc)
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def add_power_ring(self, bbox):
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@ -160,11 +160,11 @@ class pwrite_driver(design.design):
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track_xoff = self.get_m2_track(1)
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din_loc = self.din_inst.get_pin("A").center()
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self.add_via_stack("m1", "m2", din_loc)
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self.add_via_stack_center("m1", "m2", din_loc)
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din_track = vector(track_xoff,din_loc.y)
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br_in = self.br_inst.get_pin("in").center()
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self.add_via_stack("m1", "m2", br_in)
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self.add_via_stack_center("m1", "m2", br_in)
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br_track = vector(track_xoff,br_in.y)
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din_in = vector(track_xoff,0)
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@ -181,11 +181,11 @@ class pwrite_driver(design.design):
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track_xoff = self.get_m4_track(self.din_bar_track)
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din_bar_in = self.din_inst.get_pin("Z").center()
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self.add_via_stack("m1", "m3", din_bar_in)
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self.add_via_stack_center("m1", "m3", din_bar_in)
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din_bar_track = vector(track_xoff,din_bar_in.y)
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bl_in = self.bl_inst.get_pin("in").center()
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self.add_via_stack("m1", "m3", bl_in)
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self.add_via_stack_center("m1", "m3", bl_in)
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bl_track = vector(track_xoff,bl_in.y)
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din_in = vector(track_xoff,0)
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@ -204,15 +204,15 @@ class pwrite_driver(design.design):
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# This M2 pitch is a hack since the A and Z pins align horizontally
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en_bar_loc = self.en_inst.get_pin("Z").uc()
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en_bar_track = vector(track_xoff, en_bar_loc.y)
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self.add_via_stack("m1", "m3", en_bar_loc)
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self.add_via_stack_center("m1", "m3", en_bar_loc)
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# This is a U route to the right down then left
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bl_en_loc = self.bl_inst.get_pin("en_bar").center()
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bl_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack("m1", "m3", bl_en_loc)
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self.add_via_stack_center("m1", "m3", bl_en_loc)
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br_en_loc = self.br_inst.get_pin("en_bar").center()
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br_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack("m1", "m3", br_en_loc)
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self.add_via_stack_center("m1", "m3", br_en_loc)
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# L shape
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@ -237,21 +237,21 @@ class pwrite_driver(design.design):
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en_loc = self.en_inst.get_pin("A").center()
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en_rail = vector(en_loc.x, vdd_yloc)
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self.add_via_stack("m1", "m2", en_loc)
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self.add_via_stack_center("m1", "m2", en_loc)
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self.add_path("m2", [en_loc, en_rail])
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self.add_via_stack("m2", "m3", en_rail)
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self.add_via_stack_center("m2", "m3", en_rail)
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# Start point in the track on the pin rail
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en_track = vector(track_xoff, vdd_yloc)
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self.add_via_stack("m3", "m4", en_track)
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self.add_via_stack_center("m3", "m4", en_track)
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# This is a U route to the right down then left
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bl_en_loc = self.bl_inst.get_pin("en").center()
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bl_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack("m1", "m3", bl_en_loc)
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self.add_via_stack_center("m1", "m3", bl_en_loc)
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br_en_loc = self.br_inst.get_pin("en").center()
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br_en_track = vector(track_xoff, bl_en_loc.y)
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self.add_via_stack("m1", "m3", br_en_loc)
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self.add_via_stack_center("m1", "m3", br_en_loc)
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# U shape
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self.add_wire(self.m3_stack,
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