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64 Commits

Author SHA1 Message Date
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes 29da8a5209 Further changes to pbitcell so that it passes unit tests for bitcell_array 2018-08-29 15:54:49 -07:00
Michael Timothy Grimes 807a4d7767 Fixed drcs error in magic. Pbitcell should now pass unit tests in calibre and magic. 2018-08-29 15:30:50 -07:00
Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear 2018-08-29 08:52:45 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00
Matt Guthaus 8664f7a0b8 Converted all modules to not run create_layout when netlist_only 
mode is enabled.
 2018-08-27 16:42:48 -07:00
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
Michael Timothy Grimes 8c73a26daa Changing function names in bitcell and pbitcell to better reflect what values they're returning. Editting function calls in bitcell_array and bank accordingly. 2018-08-26 14:37:17 -07:00
Michael Timothy Grimes 0f8da1510e Reverting pin name changes of precharge cell and array back to 'bl' and 'br'. Also clarifying bl and br init parameters to reflect that they refer to the bitcell lines. 2018-08-18 15:27:07 -07:00
Michael Timothy Grimes af43fb6276 called bitcell function before reading the height of the bitcell because pbitcell's dynamic height can only be determined after the module is called 2018-08-15 02:19:36 -07:00
Michael Timothy Grimes 040340b49f editted naming convention on precharge to accommodate multiport 2018-08-15 02:14:45 -07:00
Matt Guthaus 34736b7b3f Remove carriage returns form python files 2018-08-07 09:44:01 -07:00
Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-05 19:53:28 -07:00
Michael Timothy Grimes 5666ee6635 altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations 2018-08-05 19:46:05 -07:00
Michael Timothy Grimes ecd4612167 altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions 2018-08-05 19:43:59 -07:00
Matt Guthaus 642a5cfe73 Line-wrap pinv debug formatting 2018-07-27 14:07:55 -07:00
Matt Guthaus e827c1b8c7 Make pinvbuf have unique names for GDS compliance. 
Add back gating of w_en since write should happen in second half
or else we will have write and precharge simultaneously active.
 2018-07-26 11:40:40 -07:00
Matt Guthaus 00a87d57ab Modified pinvbuf to have a stage effort of 4 for driving the 
clock bar to wordline enable.
Fixed comments in stimulus file to have right cycle numbers.
Removed clock gating on we signal since clock gating is already
done on the WL signals. It is redundant.
 2018-07-26 11:28:48 -07:00
Michael Timothy Grimes 7b315a3b69 updating inverter to write transistor spacings 2018-07-12 20:52:05 -07:00
Matt Guthaus ac7aa4537c Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell. 2018-06-29 11:49:02 -07:00
Matt Guthaus 69921b0844 Add enclosing well to column mux. Move well contact to cell boundary. 2018-06-29 11:35:29 -07:00
Michael Timothy Grimes fea304eac1 corrected gate to contact spacing 2018-05-31 18:31:34 -07:00
Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations 2018-05-31 17:39:51 -07:00
Michael Timothy Grimes 8f131ddb2f commiting changes from most recent pull from dev 2018-05-22 17:30:51 -07:00
Michael Timothy Grimes 17769f27c6 small changes to pbitcell 2018-05-22 14:51:42 -07:00
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit 2018-05-22 14:16:51 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Michael Timothy Grimes 7af95e4723 adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports. 2018-05-10 09:38:02 -07:00
Michael Timothy Grimes 7d3f7eefac syntax corrections to pbitcell and modifying transistor sizes 2018-04-26 14:03:03 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Michael Timothy Grimes 7f46a0dead merging changes in bitcell.py 2018-04-03 09:46:12 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Michael Timothy Grimes 0cc077598e Added member functions to bitcell.py and pbitcell.py for use in bitcell_array.py. bitcell_array now used only one function for every type of bitcell. 2018-03-15 12:02:38 -07:00