Michael Timothy Grimes c2a9e91dba Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-08-05 19:53:28 -07:00

..

pbitcell.py

altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions

2018-08-05 19:43:59 -07:00

pgate.py

Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.

2018-03-23 08:14:09 -07:00

pinv.py

Line-wrap pinv debug formatting

2018-07-27 14:07:55 -07:00

pinvbuf.py

Make pinvbuf have unique names for GDS compliance.

2018-07-26 11:40:40 -07:00

pnand2.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

pnand3.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

pnor2.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

precharge.py

altered precharge module to accomodate bitlines from pbitcell, and altered unit test to test both bitcell and pbitcell configurations

2018-08-05 19:46:05 -07:00

ptx.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

single_level_column_mux.py

Add enclosing well to column mux. Move well contact to cell boundary.

2018-06-29 11:35:29 -07:00