Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.

2018-09-13 01:42:06 -07:00

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pbitcell.py

Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.

2018-09-13 01:42:06 -07:00

pgate.py

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pinv.py

Fixed known typos of the word transition.

2018-09-10 14:27:26 -07:00

pinvbuf.py

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pnand2.py

Fixed known typos of the word transition.

2018-09-10 14:27:26 -07:00

pnand3.py

Fixed known typos of the word transition.

2018-09-10 14:27:26 -07:00

pnor2.py

Fixed known typos of the word transition.

2018-09-10 14:27:26 -07:00

precharge.py

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ptx.py

Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check.

2018-09-12 01:53:41 -07:00

replica_pbitcell.py

Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate.

2018-09-13 01:42:06 -07:00

single_level_column_mux.py

Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary.

2018-09-09 22:06:29 -07:00