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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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e19a422696886429b38ec362d0ea4b4c985f5c17
OpenRAM/compiler/pgates
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Michael Timothy Grimes e19a422696 simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations
2018-05-31 17:39:51 -07:00
..
pbitcell.py
simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations
2018-05-31 17:39:51 -07:00
pgate.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
pinv.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pinvbuf.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnand2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnand3.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
pnor2.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
precharge.py
commiting changes from most recent pull from dev
2018-05-22 17:30:51 -07:00
ptx.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
single_level_column_mux.py
commiting changes from most recent pull from dev
2018-05-22 17:30:51 -07:00
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