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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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1d5a41df2dfcc874dba4cb80dc943d1fb11ea5cd
OpenRAM/compiler/pgates
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Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear
2018-08-29 08:52:45 -07:00
..
pbitcell.py
fixed issue with read ports that caused extra transistors to appear
2018-08-29 08:52:45 -07:00
pgate.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
pinv.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
pinvbuf.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
pnand2.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
pnand3.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
pnor2.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
precharge.py
Move place function to instance class rather than hierarchy.
2018-08-27 17:25:39 -07:00
ptx.py
Converted all modules to not run create_layout when netlist_only
2018-08-27 16:42:48 -07:00
single_level_column_mux.py
Clean up new code for add_modules, add_pins and netlist/layouts.
2018-08-28 10:24:09 -07:00
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