Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
19d46f5954deedf04268c203f43d4e2ea4a08f01
OpenRAM/compiler/pgates
T
History
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
..
pbitcell.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
pgate.py
Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
2018-03-23 08:14:09 -07:00
pinv.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
pinvbuf.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
pnand2.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
pnand3.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
pnor2.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
precharge.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
ptx.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
single_level_column_mux.py
Finalized separation of netlist/layout creation.
2018-08-27 14:18:32 -07:00
Powered by Gitea Version: 1.27.2 Page: 420ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API