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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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ed8eaed54f4400df07cefdf0b17c381ca0ba9919
OpenRAM/compiler/pgates
T
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Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
..
pgate.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
pinv.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pinvbuf.py
Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
pnand2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnand3.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnor2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
ptx.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
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