OpenRAM/compiler/pgates
Michael Timothy Grimes 7af95e4723 adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports. 2018-05-10 09:38:02 -07:00
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pbitcell.py adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports. 2018-05-10 09:38:02 -07:00
pgate.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
pinv.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
pnand2.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
pnand3.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
pnor2.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
ptx.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00