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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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7af95e47230d191a6811bbf2ef079bd62b1e7558
OpenRAM/compiler/pgates
T
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Michael Timothy Grimes 7af95e4723 adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.
2018-05-10 09:38:02 -07:00
..
pbitcell.py
adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.
2018-05-10 09:38:02 -07:00
pgate.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
pinv.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnand2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnand3.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnor2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
ptx.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
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