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OpenRAM
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2597 Commits

Author SHA1 Message Date
mrg c4952ca8be Skip full sram pex test too slow 2020-10-05 13:51:20 -07:00
mrg 9fe6358569 Change .spinit to .spiceinit 2020-10-05 13:50:04 -07:00
jcirimel 5246d0a93b track s8 customs modules 2020-10-05 12:10:44 -07:00
mrg 4a58f09c1c Use 4x16 decoder with dual port bitcell in tests. 2020-10-05 10:52:56 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg f8146e3f69 Add decoder4x16 2020-10-02 15:52:09 -07:00
mrg 64cc620440 Add sram pex test 2020-10-02 14:55:10 -07:00
mrg 1fc4040607 Add pand4 and pnand4 2020-10-02 14:54:12 -07:00
mrg a62b82128c Skip riscv func test because too slow 2020-10-02 13:33:58 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
mrg aaa36bf5cf Default to 2 threads only 2020-10-01 09:55:17 -07:00
mrg d315ff18e5 Add num_threads to options. PEP8 cleanup. 2020-10-01 08:07:03 -07:00
mrg b81cdab0d6 Use unique instance names for channel routes. 2020-10-01 07:43:06 -07:00
mrg 8ce23d7f17 Provide unique WL driver instance name 2020-10-01 07:17:32 -07:00
mrg bd125e2ed3 Check for duplicate instance names. 2020-10-01 07:17:16 -07:00
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg f4e6a8895b Update riscv unit test 2020-09-30 08:50:58 -07:00
jcirimel 7cbf456a4f sky130 rba done 2020-09-30 07:34:05 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 066570bfeb Fix length of write driver 2020-09-29 16:51:55 -07:00
mrg 8e908f016e PEP8 formatting 2020-09-29 13:43:59 -07:00
mrg bca69b24e3 Optional number of functional cycles 2020-09-29 13:43:54 -07:00
mrg 54890a8d77 Add new golden data 2020-09-29 13:43:34 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg 4b5bbe755f PEP8 cleanup. Fix cur_slew bug. 2020-09-29 11:13:58 -07:00
mrg 9032bb9869 Add global wordline delay test 2020-09-29 10:28:57 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 1eb8798bb6 Add global functional test 2020-09-28 16:12:09 -07:00
mrg b2dab486fc Add draft of path exclusion calls 2020-09-28 16:05:21 -07:00
mrg 4a987bef9a Merge branch 'wlbuffer' into dev 2020-09-28 15:51:45 -07:00
mrg 159c04a25d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-09-28 15:51:35 -07:00
mrg 70c90ca7fb Replica bitcell array bbox to include unused WL gnd pins. 2020-09-28 14:49:33 -07:00
mrg 9c6d8d7aed Zjob to bottom. 2020-09-28 13:16:03 -07:00
mrg 5ab0d01779 Remove zjog and go with L shape. 2020-09-28 12:48:37 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg 6f06bb9dd5 Create sized RBL WL driver in port_address 2020-09-28 11:30:21 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
jcirimel 3dd72cdeac progress with rba pin mismatch 2020-09-23 08:37:32 -07:00
jcirimel 17e6e5eb16 row end col done 2020-09-23 08:02:56 -07:00
jcirimel 5c263e0001 rep col done w/o power pins 2020-09-23 06:24:52 -07:00
jcirimel 7afe3ea52c replica col arrangement done 2020-09-23 04:51:09 -07:00
jcirimel 7f8edf6d7c fix replica bitcell col 2020-09-23 00:36:08 -07:00
jcirimel efdc171b14 make split wl specific to each port 2020-09-23 00:08:34 -07:00
jcirimel fb6a665514 removed references to technology name 2020-09-22 18:33:03 -07:00
jcirimel de33ab3761 fix single port bitcell pattern 2020-09-22 15:08:53 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
jcirimel 559dfbc7a6 single port bitcell array done 2020-09-16 05:46:14 -07:00
mrg 392afd4d4b Add unit test for hierarchical wordline. 2020-09-15 13:46:21 -07:00
mrg 11f2b6b809 Do not do final verification if supplies were not routed 2020-09-15 13:39:00 -07:00
mrg e7ad22ff69 Separate WL via from bitell array to avoid grounded WLs 2020-09-15 13:38:28 -07:00
mrg 5e94d76127 Make global bitline only as wide as needed rather than whole array 2020-09-15 13:24:38 -07:00
mrg aff3cd2aab Update length of control bus 2020-09-15 09:49:00 -07:00
jcirimel d22164bd48 single port progess 2020-09-14 18:11:38 -07:00
mrg f25b6ffa61 Make control bus height of port data 2020-09-14 15:42:17 -07:00
mrg 7b24d1f012 Use pins for write_driver dimensions 2020-09-14 14:42:28 -07:00
mrg 55dd4d0c47 Global bitcell array working 2020-09-14 14:35:52 -07:00
mrg deaaec1ede Fix width of write enable with spare columns 2020-09-14 13:09:45 -07:00
mrg c12720a93f Extend pin correct length in new array. 2020-09-14 12:53:59 -07:00
mrg e95ab66916 Update to space according to the bitcell array. 2020-09-14 12:05:45 -07:00
mrg 4482c63d6f Fix sense amp offset index error 2020-09-11 17:12:29 -07:00
mrg 8909ad7165 Update modules to use variable bit offsets. 
Bitcell arrays can return the bit offsets.
Port data and submodules can use offsets for spacing.
Default spacing for port data if no offsets given.
 2020-09-11 15:36:22 -07:00
mrg c58741c44f Updates to global array. 
Standardize bitcell array main array offsets.
Duplicate replica interface pins in global interface pins.
 2020-09-10 16:44:54 -07:00
mrg 9c762634a5 Change default options for replica_bitcell_array 2020-09-10 15:11:48 -07:00
mrg 71d86f88b0 Merge branch 'dev' into wlbuffer 2020-09-10 13:05:14 -07:00
mrg f2313d0c73 Use default names for replica_column too 2020-09-10 12:04:46 -07:00
mrg 3c0707e5d1 Consistents of bl x port then br x port 2020-09-09 13:38:13 -07:00
mrg 3062aba214 Fix update to exclude bits with RBLs 2020-09-09 13:03:05 -07:00
mrg 12fd60e8c3 Fix pbitcell array test 2020-09-09 12:02:09 -07:00
mrg 7bb21fb73f Updates to local and global arrays to make bitline and wordlines consistent. 2020-09-09 11:54:46 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
mrg 8e91ec1770 Add check_pins function 2020-09-08 13:31:50 -07:00
mrg 1269bf6e16 Global bitcell working 2020-09-04 13:06:58 -07:00
Hunter Nichols 8bcbf005bf Merge branch 'dev' into characterizer_bug_fixes 2020-09-04 02:25:01 -07:00
Hunter Nichols 500327d59b Fixed import in simulation and fixed names in functional 2020-09-04 02:24:18 -07:00
mrg 1534295326 Ground dummy lines in replica bitcell array 2020-09-03 14:04:20 -07:00
mrg f6f6242d68 Ground dummy lines in replica bitcell array 2020-09-03 10:45:28 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
jcirimel 73443c8c95 Merge branch 'dev' into s8_single_port 2020-09-01 15:37:10 -07:00
mrg 4ec47d8ee1 Refactor global and local to be a bitcell_base_array 2020-09-01 11:59:01 -07:00
mrg c1c631abe1 Global bitcell array passes LVS/DRC 2020-09-01 10:57:49 -07:00
mrg 7bdce3ca9a Don't make dummy bitlines pins for simplicity 2020-09-01 09:55:23 -07:00
Hunter Nichols 13b1d4613c Moved spice naming checking code from design to the spice base module 2020-08-31 14:36:13 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg c1c1535210 Merge branch 'wlbuffer' into dev 2020-08-27 15:44:29 -07:00
Hunter Nichols 42f2ff679e Removed dead code from delay and base module related to characterization 2020-08-27 15:40:41 -07:00
mrg 11a82b7283 Fixed local bitcell array for single and dual port 2020-08-27 14:03:05 -07:00
mrg da827d923f Merge branch 'wlbuffer' into dev 2020-08-26 10:00:34 -07:00
mrg c321d85595 Fix syntax error for dual port 2020-08-26 09:54:41 -07:00
mrg e92337ddaf Separate get_ and get_all for bitlines and wordlines 2020-08-25 17:08:48 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bdb18b4cab Fix disconnected replica pins 2020-08-25 14:51:49 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 856cce1e62 Add -json for detailed LVS output 2020-08-25 13:58:28 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 3f45d10797 fix column decoder 2020-08-25 02:46:16 -07:00
mrg 8dee5520e0 Standardize array names independent of bitcell 2020-08-21 13:44:35 -07:00