mirror of https://github.com/VLSIDA/OpenRAM.git
Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
This commit is contained in:
mrg
parent
4b5bbe755f
commit
0c280e062a
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@ -121,4 +121,15 @@ class timing_graph():
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def __str__(self):
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""" override print function output """
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return "Nodes: {}\nEdges:{} ".format(list(self.graph), self.graph)
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str = ""
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for n in self.graph:
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str += n + "\n"
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for d in self.graph[n]:
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str += "\t\t-> " + d + "\n"
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return str
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def __repr__(self):
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""" override print function output """
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return str(self)
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@ -891,7 +891,6 @@ class delay(simulation):
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target_period = 0.5 * (ub_period + lb_period)
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# key=input("press return to continue")
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def try_period(self, feasible_delays):
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"""
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This tries to simulate a period and checks if the result
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@ -914,19 +913,19 @@ class delay(simulation):
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if self.sram.col_addr_size>0 and "slew" in dname:
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continue
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if not relative_compare(results[port][dname],feasible_delays[port][dname],error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(results[port][dname],feasible_delays[port][dname]))
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if not relative_compare(results[port][dname], feasible_delays[port][dname], error_tolerance=0.05):
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debug.info(2, "Delay too big {0} vs {1}".format(results[port][dname], feasible_delays[port][dname]))
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return False
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# key=raw_input("press return to continue")
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delay_str = ', '.join("{0}={1}ns".format(mname, results[port][mname]) for mname in self.delay_meas_names)
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debug.info(2,"Successful period {0}, Port {2}, {1}".format(self.period,
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delay_str,
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port))
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debug.info(2, "Successful period {0}, Port {2}, {1}".format(self.period,
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delay_str,
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port))
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return True
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def set_probe(self,probe_address, probe_data):
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def set_probe(self, probe_address, probe_data):
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"""
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Probe address and data can be set separately to utilize other
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functions in this characterizer besides analyze.
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@ -942,16 +941,16 @@ class delay(simulation):
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"""Calculates bitline column number of data bit under test using bit position and mux size"""
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if self.sram.col_addr_size>0:
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col_address = int(probe_address[0:self.sram.col_addr_size],2)
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col_address = int(probe_address[0:self.sram.col_addr_size], 2)
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else:
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col_address = 0
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bl_column = int(self.sram.words_per_row*probe_data + col_address)
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return bl_column
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bl_column = int(self.sram.words_per_row * probe_data + col_address)
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return bl_column
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def get_address_row_number(self, probe_address):
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"""Calculates wordline row number of data bit under test using address and column mux size"""
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return int(probe_address[self.sram.col_addr_size:],2)
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return int(probe_address[self.sram.col_addr_size:], 2)
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def prepare_netlist(self):
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""" Prepare a trimmed netlist and regular netlist. """
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@ -965,7 +964,7 @@ class delay(simulation):
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self.num_cols,
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self.word_size,
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self.num_spare_rows)
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self.trimsp.trim(self.probe_address,self.probe_data)
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self.trimsp.trim(self.probe_address, self.probe_data)
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else:
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# The non-reduced netlist file when it is disabled
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self.trim_sp_file = "{}sram.sp".format(OPTS.openram_temp)
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@ -1000,9 +999,9 @@ class delay(simulation):
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feasible_delays = self.find_feasible_period()
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# 2) Finds the minimum period without degrading the delays by X%
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self.set_load_slew(max(loads),max(slews))
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self.set_load_slew(max(loads), max(slews))
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min_period = self.find_min_period(feasible_delays)
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debug.check(type(min_period)==float,"Couldn't find minimum period.")
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debug.check(type(min_period)==float, "Couldn't find minimum period.")
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debug.info(1, "Min Period Found: {0}ns".format(min_period))
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char_sram_data["min_period"] = round_time(min_period)
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@ -1036,14 +1035,14 @@ class delay(simulation):
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self.targ_write_ports = self.write_ports
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for slew in slews:
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for load in loads:
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self.set_load_slew(load,slew)
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self.set_load_slew(load, slew)
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# Find the delay, dynamic power, and leakage power of the trimmed array.
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(success, delay_results) = self.run_delay_simulation()
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debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(self.slew,self.load))
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debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew,self.load))
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debug.check(success, "Couldn't run a simulation. slew={0} load={1}\n".format(self.slew, self.load))
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debug.info(1, "Simulation Passed: Port {0} slew={1} load={2}".format("All", self.slew, self.load))
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# The results has a dict for every port but dicts can be empty (e.g. ports were not targeted).
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for port in self.all_ports:
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for mname,value in delay_results[port].items():
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for mname, value in delay_results[port].items():
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if "power" in mname:
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# Subtract partial array leakage and add full array leakage for the power measures
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measure_data[port][mname].append(value + leakage_offset)
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@ -1064,8 +1063,8 @@ class delay(simulation):
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elif c=="1":
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inverse_address += "0"
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else:
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debug.error("Non-binary address string",1)
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return inverse_address+column_addr
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debug.error("Non-binary address string", 1)
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return inverse_address + column_addr
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def gen_test_cycles_one_port(self, read_port, write_port):
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"""Sets a list of key time-points [ns] of the waveform (each rising edge)
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@ -1075,10 +1074,10 @@ class delay(simulation):
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inverse_address = self.calculate_inverse_address()
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# For now, ignore data patterns and write ones or zeros
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data_ones = "1"*self.word_size
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data_zeros = "0"*self.word_size
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wmask_ones = "1"*self.num_wmasks
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wmask_zeroes = "0"*self.num_wmasks
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data_ones = "1" * self.word_size
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data_zeros = "0" * self.word_size
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wmask_ones = "1" * self.num_wmasks
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wmask_zeroes = "0" * self.num_wmasks
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if self.t_current == 0:
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self.add_noop_all_ports("Idle cycle (no positive clock edge)")
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@ -1094,10 +1093,10 @@ class delay(simulation):
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data_zeros,
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wmask_ones,
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times)-1
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self.measure_cycles[write_port][sram_op.WRITE_ZERO] = len(self.cycle_times) - 1
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self.add_noop_clock_one_port(write_port)
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self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times)-1
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self.measure_cycles[write_port]["disabled_write0"] = len(self.cycle_times) - 1
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# This also ensures we will have a H->L transition on the next read
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self.add_read("R data 1 address {} to set dout caps".format(inverse_address),
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@ -1107,12 +1106,11 @@ class delay(simulation):
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self.add_read("R data 0 address {} to check W0 worked".format(self.probe_address),
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self.probe_address,
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read_port)
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self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times)-1
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self.measure_cycles[read_port][sram_op.READ_ZERO] = len(self.cycle_times) - 1
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self.add_noop_clock_one_port(read_port)
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self.measure_cycles[read_port]["disabled_read0"] = len(self.cycle_times) - 1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle)")
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self.add_write("W data 1 address {} to write value".format(self.probe_address),
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@ -1120,10 +1118,10 @@ class delay(simulation):
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data_ones,
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wmask_ones,
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write_port)
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self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times)-1
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self.measure_cycles[write_port][sram_op.WRITE_ONE] = len(self.cycle_times) - 1
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self.add_noop_clock_one_port(write_port)
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self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times)-1
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self.measure_cycles[write_port]["disabled_write1"] = len(self.cycle_times) - 1
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self.add_write("W data 0 address {} to clear din caps".format(inverse_address),
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inverse_address,
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@ -1143,11 +1141,11 @@ class delay(simulation):
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self.add_read("R data 1 address {} to check W1 worked".format(self.probe_address),
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self.probe_address,
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read_port)
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self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times)-1
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self.measure_cycles[read_port][sram_op.READ_ONE] = len(self.cycle_times) - 1
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self.add_noop_all_ports("Idle cycle (if read takes >1 cycle))")
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def get_available_port(self,get_read_port):
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def get_available_port(self, get_read_port):
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"""Returns the first accessible read or write port. """
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if get_read_port and len(self.read_ports) > 0:
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@ -1169,12 +1167,12 @@ class delay(simulation):
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# Using this requires setting at least one port to target for simulation.
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if len(self.targ_write_ports) == 0 or len(self.targ_read_ports) == 0:
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debug.error("Write and read port must be specified for characterization.",1)
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debug.error("Write and read port must be specified for characterization.", 1)
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self.set_stimulus_variables()
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# Get any available read/write port in case only a single write or read ports is being characterized.
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_write_port = self.get_available_port(get_read_port=False)
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cur_read_port = self.get_available_port(get_read_port=True)
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cur_write_port = self.get_available_port(get_read_port=False)
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debug.check(cur_read_port != None, "Characterizer requires at least 1 read port")
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debug.check(cur_write_port != None, "Characterizer requires at least 1 write port")
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@ -1203,7 +1201,7 @@ class delay(simulation):
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delay = delays[0]
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for i in range(1, len(delays)):
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delay+=delays[i]
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return delay
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return delay
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def analytical_delay(self, slews, loads):
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"""
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@ -42,6 +42,8 @@ class functional(simulation):
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self.set_stimulus_variables()
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# For the debug signal names
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self.wordline_row = 0
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self.bitline_column = 0
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self.create_signal_names()
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self.add_graph_exclusions()
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self.create_graph()
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@ -15,6 +15,7 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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class timing_sram_test(openram_test):
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def runTest(self):
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@ -30,14 +31,18 @@ class timing_sram_test(openram_test):
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reload(characterizer)
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from characterizer import delay
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from sram_config import sram_config
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OPTS.local_array_size = 8
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OPTS.route_supplies = False
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c = sram_config(word_size=8,
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num_words=32,
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OPTS.local_array_size = 2
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c = sram_config(word_size=4,
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num_words=16,
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num_banks=1)
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c.words_per_row=2
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c.words_per_row=1
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c.recompute_sizes()
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# c = sram_config(word_size=8,
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# num_words=32,
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# num_banks=1)
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# c.words_per_row=2
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# c.recompute_sizes()
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debug.info(1, "Testing timing for global hierarchical array")
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s = factory.create(module_type="sram", sram_config=c)
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