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OpenRAM
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2785 Commits

Author SHA1 Message Date
mrg 3829213afe Use and2_dec instead of buf_dec for better wldriver layout 2020-12-01 11:19:12 -08:00
mrg b621c3bdc0 Allow verbose output from scripts with one -v and not unit test 2020-12-01 11:18:27 -08:00
mrg fb4cf0d4d1 Remove env variable from run_lvs script 2020-12-01 09:52:23 -08:00
mrg e817b02ade Fix syntax error. Enable script echo on -v -v. 2020-11-30 09:38:42 -08:00
Tim 'mithro' Ansell 59c6980052 Rework run_script command. 
* Use Python subprocess module.
 * Echo the command output to the console.
 * Print while things are still running.
 2020-11-29 13:03:58 -08:00
Tim 'mithro' Ansell fa5296e621 Improving magic verification shell scripts. 
* Output header at start of script.
 * Output footer at end.
 * Add a bunch more progress report to magic output.
 * Make script return the same exit code as magic.
 2020-11-29 12:19:19 -08:00
mrg 0ccb3487b6 Set default port map 2020-11-24 13:27:11 -08:00
mrg 4e10f6d8a6 Make cell/bitcell custom cell external accessible. 2020-11-24 12:01:00 -08:00
mrg cdcd115cec Fix typos 2020-11-24 10:35:14 -08:00
jcirimel d2bc7340ed finish col cap start row cap 2020-11-24 03:02:55 -08:00
jcirimel f40e5f6dba start of adding additional granularity to 1port col caps 2020-11-23 06:55:47 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg 6e51c3cda0 PEP8 cleanup bitcell_base 2020-11-22 07:11:08 -08:00
mrg 95573c858c Can redefine number of ports in custom_cell_properties 2020-11-21 08:05:49 -08:00
mrg aa03eec943 Fix syntax error. 2020-11-21 07:16:45 -08:00
mrg 4c75bc003e Fix bounding box of replica array to include wordline grounds. 2020-11-21 07:03:59 -08:00
mrg 718c327527 Fix iteration bug with new type 2020-11-20 17:33:15 -08:00
mrg e134e07522 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-20 16:57:14 -08:00
mrg f729e9fca7 Fix new replica_bitcell_array refactor with end caps. Remove single port end cap exceptions. 2020-11-20 16:56:07 -08:00
mrg 27a652ac1b Fix bounding box of cap arrays 2020-11-20 16:54:53 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
Hunter Nichols b201fa4bca Fixed path measurement in delay 2020-11-19 22:53:38 -08:00
mrg b77f168270 Fix original pin name bug in bitcell too. 2020-11-19 15:12:02 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
mrg fbed738b4a Merge multiple cell_name fix. 2020-11-18 16:27:28 -08:00
mrg 8c72d3f2e7 PEP8 and small fix 2020-11-18 14:01:25 -08:00
mrg 8507881ea8 Merge branch 's8_single_port' into dev 2020-11-18 13:59:43 -08:00
jcirimel 50a0b88ef8 fix typo 2020-11-18 11:02:40 -08:00
jcirimel 520b496611 check for cell prop names list 2020-11-18 10:47:05 -08:00
mrg 6cfa20731c Consistent naming in example configs 2020-11-18 09:59:38 -08:00
mrg 305b546ad5 PEP8 cleanup 2020-11-17 16:56:00 -08:00
mrg 02c1fac3b8 Remove partial Verilog output 2020-11-17 16:51:08 -08:00
Hunter Nichols 7a0f5e15db Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
Hunter Nichols df4c2bad1f Disabled debug measures that are WIP. 2020-11-17 13:30:18 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
Hunter Nichols eaf285639a Added debug measurements along main delay paths in SRAM. WIP. 2020-11-17 12:43:17 -08:00
mrg baae28194b Add custom cell custom port order code. Update setup/hold to use it. 2020-11-17 11:12:59 -08:00
mrg 80333ffacb Fix setup/hold characterization to use custom cell and pin names/orders. 2020-11-17 09:44:03 -08:00
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg 7512aa6e70 Skip test 50 which is too slow 2020-11-16 08:59:25 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg 1624d50ca9 Fix props bug again. 2020-11-13 20:35:19 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg b4342ac527 More cleanup 2020-11-13 17:29:20 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 3567a3e913 Remove 1rw_1r 2020-11-13 08:10:16 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 198c0faf85 Remove special s8 6t names 2020-11-13 07:45:31 -08:00
mrg 662d4ea724 Merge remote-tracking branch 'private/drclvs' into dev 2020-11-12 16:01:07 -08:00
mrg e6a7ecae84 Fix missing default path in pex 2020-11-12 14:43:57 -08:00
mrg 9eeab14639 Add comment before pininfo 2020-11-12 14:33:42 -08:00
mrg bdda7c4f5f Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
mrg 190234df58 Add PININFO to outputs too 2020-11-12 12:12:53 -08:00
mrg 63941a10e1 Add None as sp_file parameter to local_drc_check 2020-11-12 10:01:38 -08:00
mrg d4c4658c77 Clean up invalid routing layer error message 2020-11-12 09:43:08 -08:00
mrg d3cb22c8c1 Fix pin vs module names issue #26 2020-11-12 09:33:48 -08:00
mrg 537e862d48 Add -full to LVS script 2020-11-10 20:38:41 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 31ae56ff39 Simplify to a single DRC/LVS library test. 2020-11-10 16:45:00 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 56c2222c2b Temp comment Magic GDS filter code. 2020-11-10 13:37:18 -08:00
mrg 57e708a6e1 Add 200 cycles. Can be commented out or run for shorter. 2020-11-09 15:20:36 -08:00
mrg 2c203530ad Merge branch 'drclvs' into dev 2020-11-09 14:36:36 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg e31cbeaa6f Don't check for file to determine if it is included. 2020-11-09 12:11:47 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 31d21e169f Skip LEF test as correct output keeps changing. 2020-11-09 11:14:55 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2da9c307db Disable 4x16 decoder test for now 2020-11-06 13:50:04 -08:00
mrg 147649e142 Why was single port decoder test a dual port? 2020-11-06 12:21:30 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg 18d2987805 Cleanup 2020-11-05 16:30:15 -08:00
mrg a40716dd48 Cleanup imports 2020-11-05 14:32:08 -08:00
mrg 0118b73eec Cleanup imports 2020-11-05 14:31:53 -08:00
mrg 681b3a91aa Drop to debug in debug module when -d 2020-11-05 13:20:54 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg a52aac5f31 Add gds flatten option for Magic 2020-11-05 13:12:08 -08:00
mrg ce7be7466f Model as subckt for Magic too 2020-11-05 13:11:36 -08:00
mrg b160c4a35d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 14:31:42 -08:00
mrg 9a38f7a5f4 Enable gds readonly in Magic DRC/LVS 2020-11-04 10:50:53 -08:00
mrg fb0b285652 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 10:40:20 -08:00
mrg 6e12d4d46c Skip tri gate array test 2020-11-04 06:57:51 -08:00
Matt Guthaus 844b850b74 Fix typo in 1w_1r bitcell 2020-11-03 17:14:45 -08:00
mrg 3315fe32ba Improve nominal corner message 2020-11-03 16:49:49 -08:00
mrg 45cdecdea9 Improve error message about missing DRC/LVS tools. 2020-11-03 15:47:04 -08:00
mrg 6335bc3784 Do not drop to pdb shell when verbose 2020-11-03 15:46:46 -08:00
mrg 29f4ee492b Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00