mrg 033111a5f3 Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

..

base

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

bitcells

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

characterizer

Add custom cell custom port order code. Update setup/hold to use it.

2020-11-17 11:12:59 -08:00

custom

Small fix for finding pin names in timing graph.

2020-11-16 13:57:31 -08:00

datasheet

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drc

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example_configs

Consistent naming in example configs

2020-11-18 09:59:38 -08:00

gdsMill

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modules

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

pgates

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

riscv

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router

Adjust openram options.

2020-11-05 13:12:26 -08:00

sram

Add 200 cycles. Can be commented out or run for shorter.

2020-11-09 15:20:36 -08:00

tests

Skip test 50 which is too slow

2020-11-16 08:59:25 -08:00

verify

Fix missing default path in pex

2020-11-12 14:43:57 -08:00

debug.py

Cleanup imports

2020-11-05 14:32:08 -08:00

gen_stimulus.py

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globals.py

Rework bitcells.

2020-11-13 10:07:40 -08:00

Makefile

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openram.py

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options.py

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

run_profile.sh

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sram_factory.py

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

view_profile.py

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