| .. |
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base
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Set default port map
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2020-11-24 13:27:11 -08:00 |
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bitcells
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Many edits.
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2020-11-22 08:24:47 -08:00 |
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characterizer
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Fixed issue with selection of column address when checking bitline names.
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2020-11-20 01:11:08 -08:00 |
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custom
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Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.
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2020-11-17 15:05:07 -08:00 |
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datasheet
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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drc
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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example_configs
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Consistent naming in example configs
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2020-11-18 09:59:38 -08:00 |
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gdsMill
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start of adding additional granularity to 1port col caps
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2020-11-23 06:55:47 -08:00 |
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modules
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Make cell/bitcell custom cell external accessible.
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2020-11-24 12:01:00 -08:00 |
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pgates
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Merge branch 'dev' into characterizer_bug_fixes
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2020-11-20 11:16:41 -08:00 |
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riscv
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single port progess
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2020-09-14 18:11:38 -07:00 |
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router
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Adjust openram options.
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2020-11-05 13:12:26 -08:00 |
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sram
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Merged with dev
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2020-11-10 15:47:56 -08:00 |
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tests
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-11-20 16:57:14 -08:00 |
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verify
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Fix missing default path in pex
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2020-11-12 14:43:57 -08:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Cleanup imports
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2020-11-05 14:32:08 -08:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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Rework bitcells.
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2020-11-13 10:07:40 -08:00 |
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openram.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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options.py
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Set default port map
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2020-11-24 13:27:11 -08:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Read different modules overrides for different num ports
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2020-11-06 11:09:50 -08:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
0ccb3487b6