mrg 27a652ac1b Fix bounding box of cap arrays

2020-11-20 16:54:53 -08:00

..

base

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

bitcells

Fix original pin name bug in bitcell too.

2020-11-19 15:12:02 -08:00

characterizer

Add custom cell custom port order code. Update setup/hold to use it.

2020-11-17 11:12:59 -08:00

custom

Small fix for finding pin names in timing graph.

2020-11-16 13:57:31 -08:00

datasheet

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

drc

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

example_configs

Consistent naming in example configs

2020-11-18 09:59:38 -08:00

gdsMill

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

modules

Fix bounding box of cap arrays

2020-11-20 16:54:53 -08:00

pgates

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Adjust openram options.

2020-11-05 13:12:26 -08:00

sram

Add 200 cycles. Can be commented out or run for shorter.

2020-11-09 15:20:36 -08:00

tests

Skip test 50 which is too slow

2020-11-16 08:59:25 -08:00

verify

Fix missing default path in pex

2020-11-12 14:43:57 -08:00

debug.py

Cleanup imports

2020-11-05 14:32:08 -08:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Rework bitcells.

2020-11-13 10:07:40 -08:00

Makefile

Clean up Makefile for unit tests

2018-12-05 12:58:10 -08:00

openram.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

options.py

Default to no hierarchical word lines.

2020-11-19 10:48:35 -08:00

run_profile.sh

Convert pin map to a set for faster membership.

2019-04-01 15:45:44 -07:00

sram_factory.py

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00