OpenRAM/compiler
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
..
base Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
bitcells Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
characterizer Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
custom Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
datasheet Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
drc Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
example_configs Consistent naming in example configs 2020-11-18 09:59:38 -08:00
gdsMill Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
modules Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
pgates Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
riscv single port progess 2020-09-14 18:11:38 -07:00
router Adjust openram options. 2020-11-05 13:12:26 -08:00
sram Merged with dev 2020-11-10 15:47:56 -08:00
tests Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
verify Fix missing default path in pex 2020-11-12 14:43:57 -08:00
Makefile
debug.py Cleanup imports 2020-11-05 14:32:08 -08:00
gen_stimulus.py Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
globals.py Rework bitcells. 2020-11-13 10:07:40 -08:00
openram.py Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
options.py Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
run_profile.sh
sram_factory.py Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
view_profile.py