mrg 5ee3f4cc66 Many edits. ...

Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.

2020-11-22 08:24:47 -08:00

..

base

Many edits.

2020-11-22 08:24:47 -08:00

bitcells

Many edits.

2020-11-22 08:24:47 -08:00

characterizer

Fixed issue with selection of column address when checking bitline names.

2020-11-20 01:11:08 -08:00

custom

Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later.

2020-11-17 15:05:07 -08:00

datasheet

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

drc

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

example_configs

Consistent naming in example configs

2020-11-18 09:59:38 -08:00

gdsMill

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

modules

Many edits.

2020-11-22 08:24:47 -08:00

pgates

Merge branch 'dev' into characterizer_bug_fixes

2020-11-20 11:16:41 -08:00

riscv

single port progess

2020-09-14 18:11:38 -07:00

router

Adjust openram options.

2020-11-05 13:12:26 -08:00

sram

Merged with dev

2020-11-10 15:47:56 -08:00

tests

Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev

2020-11-20 16:57:14 -08:00

verify

Fix missing default path in pex

2020-11-12 14:43:57 -08:00

debug.py

Cleanup imports

2020-11-05 14:32:08 -08:00

gen_stimulus.py

Fixed errors in extra rows characterization

2020-03-22 20:54:49 +00:00

globals.py

Rework bitcells.

2020-11-13 10:07:40 -08:00

Makefile

…

openram.py

Remove EOL whitespace globally

2020-11-03 06:29:17 -08:00

options.py

Many edits.

2020-11-22 08:24:47 -08:00

run_profile.sh

…

sram_factory.py

Read different modules overrides for different num ports

2020-11-06 11:09:50 -08:00

view_profile.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00