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base
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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bitcells
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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characterizer
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Fix errors in new run_sim calls and corners
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2020-11-09 13:59:46 -08:00 |
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custom
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More cleanup
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2020-11-13 17:29:20 -08:00 |
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datasheet
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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drc
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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example_configs
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Create single port memory config examples.
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2020-11-03 14:42:56 -08:00 |
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gdsMill
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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modules
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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pgates
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Read different modules overrides for different num ports
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2020-11-06 11:09:50 -08:00 |
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riscv
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single port progess
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2020-09-14 18:11:38 -07:00 |
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router
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Adjust openram options.
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2020-11-05 13:12:26 -08:00 |
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sram
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Add 200 cycles. Can be commented out or run for shorter.
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2020-11-09 15:20:36 -08:00 |
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tests
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Change custom cells to use set_ports setter
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2020-11-14 07:15:27 -08:00 |
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verify
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Fix missing default path in pex
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2020-11-12 14:43:57 -08:00 |
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Makefile
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…
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debug.py
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Cleanup imports
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2020-11-05 14:32:08 -08:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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Rework bitcells.
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2020-11-13 10:07:40 -08:00 |
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openram.py
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Remove EOL whitespace globally
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2020-11-03 06:29:17 -08:00 |
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options.py
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Rework bitcells.
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2020-11-13 10:07:40 -08:00 |
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run_profile.sh
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…
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sram_factory.py
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Read different modules overrides for different num ports
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2020-11-06 11:09:50 -08:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
2f994b8c0a