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OpenRAM
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241 Commits

Author SHA1 Message Date
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Aditi Sinha 5c50cf234b Fixed lvs errors for spare columns 2020-05-09 07:56:19 +00:00
Aditi Sinha e30938fb66 Spare columns working at bank level 2020-05-03 15:23:30 +00:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
mrg 1a2efd77ad Move rbl route away from bitcell array 2020-03-06 09:48:20 -08:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg 9c1f0657dd PEP8 Formatting 2020-03-05 11:58:36 -08:00
Aditi Sinha 694ea5c20e Characterization for extra rows 2020-02-20 17:31:58 +00:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Bastian Koppelmann 64bf93e4e5 bank: Connect instances by their individual bl/br names 
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
mrg 2ff058f5d5 PEP8 Cleanup and reverse pitch offset of col addr routing 2020-02-06 22:59:30 +00:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Aditi Sinha 5b3846e1e5 Changed replica bitcell array to work with bank tests for non power of two rows 2019-12-08 13:24:39 +00:00
jsowash 1a72070f04 Removed LVS error where w_en went over whole AND array in 2 port. 2019-09-03 17:14:31 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Matt Guthaus 34d28a19e6 Connect wl_en in all ports to bank. 2019-08-10 12:30:23 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Matt Guthaus ae46a464b9 Undo delay changes. Fix bus order for DRC. 2019-08-06 17:17:59 -07:00
Matt Guthaus a2f81aeae4 Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. 2019-08-06 16:29:07 -07:00
Matt Guthaus 8771ffbfed Fix bug to add all p_en_bar to banks 2019-08-01 12:28:21 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus fb60b51c72 Add check bits. Clean up logic. Move read/write bit check to next cycle. 2019-07-24 16:57:04 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
Matt Guthaus 07401fc6ea Make control bus routing offset consistent 2019-07-23 09:39:28 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
mrg b546ecce2c Check 2 ports only for layout. 2019-07-16 14:11:54 -07:00
mrg 12fa36317e Cleanup unit test. Fix s_en control bug for r-only. 2019-07-16 13:51:31 -07:00
mrg 2f55911604 Simplify column decoder placement. 2019-07-16 11:55:25 -07:00
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
mrg e550d6ff10 Port name maps between bank and replica array working. 2019-07-15 11:29:29 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg 0b13225913 Single banks working with new RBL 2019-07-11 14:47:27 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg 9dab0be737 Single bank working with replica array. 2019-07-05 13:44:29 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash f29631695c Finished merge 2019-07-05 11:43:31 -07:00
mrg bfe4213fce Port address added to entire SRAM. 2019-07-05 09:44:42 -07:00
mrg c0f9cdbc12 Create port address module 2019-07-05 09:03:52 -07:00
jsowash 02a0cd71ac fixed merge conflict 2019-07-04 11:14:32 -07:00
Matt Guthaus 0cb86b8ba2 Exclude new precharge in graph build 2019-07-03 14:46:20 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00
mrg bc4a3ee2b7 New port_data module works in SCMOS 2019-07-03 13:17:12 -07:00
mrg 244604fb0d Data port module working by itself. 2019-07-02 15:35:53 -07:00
mrg 2abe859df1 Fix shared bank offset. 2019-07-01 16:29:59 -07:00
jsowash 242771f710 Merge branch 'dev' into add_wmask 2019-06-28 15:44:27 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Hunter Nichols ce7e320505 Undid change to add bitcell as input to array mod. 2019-06-25 18:26:13 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
mrg 4523a7b9f6 Replica bitcell array working 2019-06-19 16:03:21 -07:00
Hunter Nichols 2b07db33c8 Added bitcell as input to array, but there are DRC errors now. 2019-06-17 15:31:16 -07:00
Matt Guthaus 6e044b776f Merge branch 'pep8_cleanup' into dev 2019-06-14 08:47:10 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
mrg 301f032619 Remove +1 to induce error. 2019-05-31 10:55:17 -07:00
mrg d789f93743 Add debug runner during individual tests. 2019-05-31 10:51:42 -07:00
Hunter Nichols 099bc4e258 Added bitcell check to storage nodes. 2019-05-20 18:35:52 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols a500d7ee3d Adjusted bitcell analytical delays for multiport cells. 2019-04-09 02:49:52 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols cc5b347f42 Added analyical model test which compares measured delay to model delay. 2019-04-03 16:26:20 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Matt Guthaus 881c449c7c Fix error in offset computation for right drivers 2019-01-28 07:53:36 -08:00
Matt Guthaus c4438584fe Move jog for wl to mid-cells rather than mid-pins. 2019-01-27 12:59:02 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 3c4d559308 Fixed syntax error referring to column mux 2018-11-29 13:29:16 -08:00
Matt Guthaus 3d3f54aa86 Add col addr line spacing for col addr decoder 2018-11-29 13:22:48 -08:00
Matt Guthaus 4df862d8af Convert channel router to take netlist of pins rather than names. 2018-11-29 12:12:10 -08:00
Matt Guthaus 02a67f9867 Missing gap in port 1 col decoder 2018-11-28 18:07:31 -08:00
Matt Guthaus d041a498f3 Fix height of port 1 control bus. Adjust column decoder names. 2018-11-28 17:48:25 -08:00
Matt Guthaus a2a9cea37e Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
Matt Guthaus d99dcd33e2 Fix SRAM level control routing errors. 2018-11-28 15:30:52 -08:00
Matt Guthaus b5b691b73d Fix missing via in clk input of control 2018-11-28 13:20:39 -08:00
Matt Guthaus c43a140b5e All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00