mirror of https://github.com/VLSIDA/OpenRAM.git
Fix bug to add all p_en_bar to banks
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@ -100,7 +100,8 @@ class bank(design.design):
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self.add_pin("bank_sel{}".format(port),"INPUT")
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for port in self.read_ports:
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self.add_pin("s_en{0}".format(port), "INPUT")
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self.add_pin("p_en_bar{0}".format(port), "INPUT")
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for port in self.all_ports:
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self.add_pin("p_en_bar{0}".format(port), "INPUT")
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for port in self.write_ports:
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self.add_pin("w_en{0}".format(port), "INPUT")
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for bit in range(self.num_wmasks):
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