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OpenRAM
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961 Commits

Author SHA1 Message Date
samuelkcrow 231dca5b51 route w_en A and B inputs via M3, fix delay chain outputs connection to vertical bus 2022-07-21 19:35:02 -07:00
samuelkcrow 74bf3770d9 move pins to m3, route in pin down to avoid m3 collision 2022-07-21 19:35:02 -07:00
samuelkcrow fd7a7c2564 routing mistake in route_wlen 2022-07-21 19:35:02 -07:00
samuelkcrow 1e1ec54275 fix indentation errors, typos, and missing iterator 2022-07-21 19:35:02 -07:00
samuelkcrow 3526a57864 don't route rbl to conrol logic 2022-07-21 19:35:02 -07:00
samuelkcrow 1d6bd78612 multi-delay layout pins and routing for them in control logic 2022-07-21 19:35:01 -07:00
samuelkcrow d7b1368115 all route functions except for delay 2022-07-21 19:35:01 -07:00
samuelkcrow 63ea1588c1 more consise glitch names, remove pre_sen from vertical bus, typo in glitch2 placement 2022-07-21 19:35:01 -07:00
samuelkcrow 0a3c1dd9b8 remove pre_sen entirely, move inverter to wl_en row, complete placement functions 2022-07-21 19:35:01 -07:00
samuelkcrow 7b4af87fda remove the cs_buf function call... smh 2022-07-21 19:35:01 -07:00
samuelkcrow 5edb511dab try it without pre_sen 2022-07-21 19:35:01 -07:00
samuelkcrow 71f241f660 remove remaining cs_buf functions 2022-07-21 19:35:01 -07:00
samuelkcrow 67c1560df0 forgot other place with cs_buf 2022-07-21 19:35:01 -07:00
samuelkcrow fede082b80 cs instead of cs_buf now that everything else is working 2022-07-21 19:35:01 -07:00
samuelkcrow 30b9c2fc25 remove glitch inverters from placement functions, move glitch1 to pen row 2022-07-21 19:35:01 -07:00
samuelkcrow 606260dd68 use odd number inverter chains from delay chain for delay instead of external inverters 2022-07-21 19:35:01 -07:00
samuelkcrow b9b57ab6b3 double length of delay chain as well 2022-07-21 19:35:01 -07:00
samuelkcrow 06254fae72 forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops 2022-07-21 19:35:01 -07:00
samuelkcrow ef2c9fe296 exclude rbl connection in sram base for delay control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 7d4b718344 add most functions needed for delay control logic, fix multi-delay pin order issue 2022-07-21 19:35:01 -07:00
samuelkcrow 45239ca2a9 use cs_buf for sense amp on r ports instead of cs 2022-07-21 19:35:01 -07:00
samuelkcrow c4138c9f9b typo in cs buf netlist function 2022-07-21 19:35:01 -07:00
samuelkcrow 2b72fbee4e bug fix list vs set 2022-07-21 19:35:01 -07:00
samuelkcrow 11ea82e782 check delay chain pinout list, add cs_buf to control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 78013d32b7 hard-code multi-delay stages 2022-07-21 19:35:01 -07:00
samuelkcrow 62a65f8053 all remaining spice for delay control 2022-07-21 19:35:01 -07:00
samuelkcrow 66502fc5dc new control logic module with no more rbl logic, added glitches so far 2022-07-21 19:35:01 -07:00
samuelkcrow b05a721fb5 spice for delay chain with all inverter outputs as pins 2022-07-21 19:35:01 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg cf03454ecf Don't add wdriver_sel_n pins which aren't used. 2022-06-10 09:18:40 -07:00
mrg d30f05a1ae Update power layer on li for sky130 2022-06-08 17:19:26 -07:00
mrg 280582d4d6 Add missing via in dff array 2022-06-08 14:24:17 -07:00
mrg ad6633ddca Update versions of tools. Fix supply bug in predecode. 2022-06-08 13:50:25 -07:00
mrg 8c85230033 Remove experimental power option. 2022-05-23 10:08:35 -07:00
mrg 735d66c9f1 Start dff array supplies on first rather than second bit. 2022-05-17 15:54:54 -07:00
mrg 3e02a0e7df Update column decoder and dff array supplies 2022-05-17 15:49:50 -07:00
mrg f1f4453d14 Add column decoder module with power supply straps. 2022-05-17 13:32:19 -07:00
mrg 9b592ab432 Fix missing hash recompute in vector class. 2022-05-17 13:30:41 -07:00
mrg bdd334bce9 Add layer and directions to pbitcell 2022-05-16 16:11:13 -07:00
mrg 4345136d1a Fix offsets for local bitcell arrays. 2022-05-13 10:46:00 -07:00
mrg 357f967a93 Leave supply routing to new helper functions. 2022-05-11 11:01:14 -07:00
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently. 2022-05-09 11:44:46 -07:00
mrg 50045e54e8 Fix a couple supply routing issues. 2022-05-03 11:45:51 -07:00
mrg f8f3f16b1f Move delay line supply strap for pin access. 2022-05-02 16:42:14 -07:00
mrg b1bb9151c4 Reimplement off grid pins. 
Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
 2022-05-02 15:43:14 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 5e546ee974 New power strapping mostly working. 
Each module uses M3/M4 power straps with pins on the ends.
Works in all technologies for a single no mux, dual port SRAM.
 2022-04-05 13:51:55 -07:00
mrg 01a73b31e1 Fix power ring routing boundary bug. 2022-03-18 10:32:25 -07:00