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151 Commits

Author SHA1 Message Date
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols 6b8d143073 Changed cacti RC delay function to better match cacti code in bitcell. Sense amp also has similar changed but is missing transconductance parameter. 2021-09-01 14:27:13 -07:00
Hunter Nichols 680d7b5d93 Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined. 2021-08-25 16:12:05 -07:00
Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values. 2021-08-01 19:25:54 -07:00
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files. 2021-07-21 14:59:02 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols 2c9f755a73 Added on resistance functions for pgates, custom cells, and bitcell. 2021-07-12 14:25:37 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols b408a871f9 Added direction information functions to 2-port bitcell modules 2021-06-21 17:19:15 -07:00
Hunter Nichols 16e658726e When determining bitline names, added a technology check for sky130. 2021-06-16 17:04:02 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 6062565973 Add col/row cap modules 2020-12-08 10:34:24 -08:00
mrg 5ee3f4cc66 Many edits. 
Use internal vdd/gnd names.
Refactor getters in bitcell to base class.
Add BIAS signal type.
 2020-11-22 08:24:47 -08:00
mrg 6e51c3cda0 PEP8 cleanup bitcell_base 2020-11-22 07:11:08 -08:00
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
mrg b77f168270 Fix original pin name bug in bitcell too. 2020-11-19 15:12:02 -08:00
mrg 35c162acbd Use internal pin names in path names for signal traces. 2020-11-19 08:45:09 -08:00
Hunter Nichols 7a0f5e15db Added polarity checks in modules to allow to make it easier to get spice rise/fall. Path measures not failing now but should be changed later. 2020-11-17 15:05:07 -08:00
mrg 902b92223f Small fix for finding pin names in timing graph. 2020-11-16 13:57:31 -08:00
mrg 86799ae3ff Small bug fixes related to new name mapping. 2020-11-16 13:42:42 -08:00
mrg 1d729e8f02 Move pin name mapping to layout class. 2020-11-16 11:04:03 -08:00
mrg 93e94e26ec Get vdd/gnd from properties if it is defined. 2020-11-16 10:14:37 -08:00
mrg e4bc2c4914 Update property settings with getters/setters 2020-11-14 08:08:42 -08:00
mrg 2f994b8c0a Change custom cells to use set_ports setter 2020-11-14 07:15:27 -08:00
mrg e9420d57c2 Fix missing attributes 2020-11-13 19:04:26 -08:00
mrg b4342ac527 More cleanup 2020-11-13 17:29:20 -08:00
mrg a2b17a271c Port type order generated on the fly 2020-11-13 16:41:02 -08:00
mrg 01d191da40 clk_pin is redundant in DFFs 2020-11-13 16:23:27 -08:00
mrg 620e271562 Fix various typos and errors 2020-11-13 16:04:07 -08:00
mrg 8021430122 Fix pbitcell erros 2020-11-13 15:55:55 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 3567a3e913 Remove 1rw_1r 2020-11-13 08:10:16 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 29f4ee492b Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00
mrg fb9956fe96 Fix missing include 2020-11-03 13:50:45 -08:00
mrg d209e8d9a3 Disable perimeter pins for now 2020-11-03 13:35:34 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg a128e0501e Use cell_name in col and row caps too. 2020-11-03 12:10:18 -08:00
mrg 87419bd640 Fix bitcell and pbitcell with different cell names 2020-11-03 11:30:40 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg aec5865d71 Fix base class error 2020-11-02 17:41:14 -08:00
mrg f9787eb878 Use bitcell_base for all bitcells. Fix missing setup_bitcell call 2020-11-02 17:00:15 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
Tim 'mithro' Ansell bb164d915d Allow overriding the cell size layer name. 2020-11-02 10:03:52 -08:00
Tim 'mithro' Ansell 6514bcb4c1 Use default bitcell name if one isn't provided. 
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:52:00 -08:00
Tim 'mithro' Ansell 5c1250191c Fixup the bitcell.py to make subclassing work. 
Read in the GDS properties inside the __init__ method.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
 2020-11-02 09:51:54 -08:00
mrg acfec369d6 Add ptx cell properties 2020-10-28 09:54:15 -07:00
mrg 07ef43eaf8 Convert design class data to static 2020-10-27 09:23:11 -07:00
mrg 20be7caf98 Make conditional wl and bl for dummy rows/cols. 2020-10-15 13:56:37 -07:00
mrg fcb7f42e48 Remove split_wl 2020-10-12 17:27:20 -07:00