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Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

This commit is contained in:
Hunter Nichols 2021-09-07 15:56:27 -07:00
parent 6b8d143073
commit 1236a0773a
7 changed files with 19 additions and 15 deletions
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6
compiler/base/hierarchy_spice.py
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@ -430,7 +430,9 @@ class spice():
r_wire = self.module_wire_r()
tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2)
extra_param_dict={'vdd': corner[1]} #voltage is second in PVT corner
extra_param_dict = {}
extra_param_dict['vdd'] = corner[1] #voltage is second in PVT corner
extra_param_dict['load'] = c_wire+c_intrinsic+c_load #voltage is second in PVT corner
this_delay = self.cacti_rc_delay(inrisetime, tf, 0.5, 0.5, True, extra_param_dict)
inrisetime = this_delay / (1.0 - 0.5)
return delay_data(this_delay, inrisetime)
@ -526,7 +528,7 @@ class spice():
vs2, # threshold voltage
rise, # whether input rises or fall
extra_param_dict=None):
) """By default, CACTI delay uses horowitz for gate delay.
"""By default, CACTI delay uses horowitz for gate delay.
Can be overriden in cases like bitline if equation is different.
"""
return self.horowitz(inputramptime, tf, vs1, vs2, rise)

1
compiler/base/timing_graph.py
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@ -122,6 +122,7 @@ class timing_graph():
if params["model_name"] == "cacti":
delays.append(path_edge_mod.cacti_delay(corner, cur_slew, cout, params))
cur_slew = delays[-1].slew
elif params["model_name"] == "elmore":
delays.append(path_edge_mod.analytical_delay(corner, cur_slew, cout))
else:

6
compiler/bitcells/bitcell_base.py
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@ -241,7 +241,6 @@ class bitcell_base(design.design):
# graph implementation so array dims are all re-calculated here. May
# be incorrect if dim calculations change
cells_in_col = OPTS.num_words/OPTS.words_per_row
debug.info(0,"l={}".format(cells_in_col*self.height))
return cells_in_col*self.height*spice["wire_c_per_um"]
def module_wire_r(self):
@ -253,15 +252,16 @@ class bitcell_base(design.design):
return cells_in_col*self.height*spice["wire_r_per_um"]
def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise, extra_param_dict):
) """ Special RC delay function used by CACTI for bitline delay
""" Special RC delay function used by CACTI for bitline delay
"""
import math
vdd = extra_param_dict['vdd']
m = vdd / inrisetime #v_wl = vdd for OpenRAM
m = vdd / inputramptime #v_wl = vdd for OpenRAM
# vdd == V_b_pre in OpenRAM. Bitline swing is assumed 10% of vdd
tstep = tf * math.log(vdd/(vdd - 0.1*vdd))
if tstep > 0.5*(vdd-spice["nom_threshold"])/m:
delay = tstep + (vdd-spice["nom_threshold"])/(2*m)
else:
delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m)
return delay

4
compiler/characterizer/cacti.py
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@ -76,10 +76,8 @@ class cacti(simulation):
#load_farad = 0.052275e-12
slew = 0
path_delays = self.graph.get_timing(bl_path, self.corner, slew, load_farad, self.params)
total_delay = self.sum_delays(path_delays)
#debug.info(0, "total_delay={}".format(total_delay))
#sys.exit()
delay_ns = total_delay.delay/1e-9
slew_ns = total_delay.slew/1e-9
max_delay = max(max_delay, total_delay.delay)

9
compiler/custom/sense_amp.py
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@ -7,7 +7,7 @@
#
import design
import debug
from tech import parameter, drc
from tech import parameter, drc, spice
from tech import cell_properties as props
import logical_effort
@ -110,14 +110,11 @@ class sense_amp(design.design):
return nmos_drain_c + pmos_drain_c + bl_pmos_drain_c
def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise, extra_param_dict):
) """ Special RC delay function used by CACTI for sense amp delay
""" Special RC delay function used by CACTI for sense amp delay
"""
import math
# FIXME: temp values
c_senseamp = extra_param_dict['load']
vdd = extra_param_dict['vdd']
g_m = 1
tau = c_senseamp/g_m
v_sense = 1
tau = c_senseamp/spice["sa_transconductance"]
return tau*math.log(vdd/(0.1*vdd))

4
technology/freepdk45/tech/tech.py
View File

@ -470,7 +470,9 @@ spice["c_junc"] = 5e-16 #F/um^2
spice["c_junc_sw"] = 5e-16 #F/um
spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units
spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units
spice["mobility_n"] = 0.045e8 # um^2/(V*s)
spice["V_dsat"] = 0.0938 # From CACTI 45nm tech
spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa_inv_nmos_size"]/_lambda_)*spice["V_dsat"]
###################################################
# Technology Tool Preferences
###################################################

4
technology/scn4m_subm/tech/tech.py
View File

@ -416,6 +416,10 @@ spice["c_junc"] = 9.276962e-16 #F/um^2
spice["c_junc_sw"] = 3.181055e-16 #F/um
spice["wire_c_per_um"] = spice["wire_unit_c"]*drc["minwidth_m2"] # Unit c by m2 width, F/um units
spice["wire_r_per_um"] = spice["wire_unit_r"]/drc["minwidth_m2"] # Unit r per m2 width, Ohms/um units
spice["mobility_n"] = 444.94e8 # um^2/(V*s)
spice["V_dsat"] = 0.256 # From CACTI 180nm tech
spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa_inv_nmos_size"]/_lambda_)*spice["V_dsat"]
###################################################
# Technology Tool Preferences