mirror of https://github.com/VLSIDA/OpenRAM.git
Added direction information functions to 2-port bitcell modules
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@ -99,3 +99,8 @@ class bitcell_2port(bitcell_base.bitcell_base):
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# Port 1 edges
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graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
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graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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@ -49,3 +49,8 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
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# Port 1 edges
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graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
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graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
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def is_non_inverting(self):
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"""Return input to output polarity for module"""
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return False
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