Added on resistance functions for pgates, custom cells, and bitcell.

compiler/base/hierarchy_spice.py

@@ -515,7 +515,7 @@ class spice():
 
         return td
   
-    def tr_r_on(width, nchannel, stack, _is_cell):
+    def tr_r_on(width, is_nchannel, stack, _is_cell):
 
         # FIXME: temp code until parameters have been determined
         if _is_cell:
@@ -524,7 +524,7 @@ class spice():
             dt = tech.peri_global
       
 
-        restrans = dt.R_nch_on if nchannel else dt.R_pch_on
+        restrans = dt.R_nch_on if is_nchannel else dt.R_pch_on
         return stack * restrans / width
 
     def gate_c(width, wirelength, _is_cell)

compiler/bitcells/bitcell_base.py

@@ -202,3 +202,9 @@ class bitcell_base(design.design):
         debug.check(port == 0, "One port for bitcell only.")
         return "wl"
 
+    def get_on_resistance(self):
+        """On resistance of pinv, defined by single nmos"""
+        is_nchannel = True
+        stack = 2 # for access and inv tx
+        is_cell = False
+        return self.tr_r_on(drc["minwidth_tx"], is_nchannel, stack, is_cell)    

compiler/custom/nand2_dec.py

@@ -74,3 +74,10 @@ class nand2_dec(design.design):
         """Return input to output polarity for module"""
 
         return False
+
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 2
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)   

compiler/custom/nand3_dec.py

@@ -74,3 +74,10 @@ class nand3_dec(design.design):
         """Return input to output polarity for module"""
 
         return False
+
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 3
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)  

compiler/custom/nand4_dec.py

@@ -74,3 +74,10 @@ class nand4_dec(design.design):
         """Return input to output polarity for module"""
 
         return False
+
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 4
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)  

compiler/custom/sense_amp.py

@@ -79,3 +79,10 @@ class sense_amp(design.design):
         
         #FIXME: This only applied to bl/br -> dout and not s_en->dout
         return True     
+
+    def get_on_resistance(self):
+        """On resistance of pinv, defined by single nmos"""
+        is_nchannel = False
+        stack = 1
+        is_cell = False
+        return self.tr_r_on(parameter["sa_inv_nmos_size"], is_nchannel, stack, is_cell)    

compiler/pgates/pinv.py

@@ -342,3 +342,10 @@ class pinv(pgate.pgate):
         """Return input to output polarity for module"""
         
         return False    
+
+    def get_on_resistance(self):
+        """On resistance of pinv, defined by single nmos"""
+        is_nchannel = True
+        stack = 1
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)    

compiler/pgates/pnand2.py

@@ -318,4 +318,12 @@ class pnand2(pgate.pgate):
     def is_non_inverting(self):
         """Return input to output polarity for module"""
         
-        return False
+        return False
+        
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 2
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)    
+        

compiler/pgates/pnand3.py

@@ -351,4 +351,11 @@ class pnand3(pgate.pgate):
     def is_non_inverting(self):
         """Return input to output polarity for module"""
         
-        return False
+        return False
+        
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 3
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)        

compiler/pgates/pnand4.py

@@ -369,3 +369,10 @@ class pnand4(pgate.pgate):
         Overrides base class function.
         """
         self.add_graph_edges(graph, port_nets)
+
+    def get_on_resistance(self):
+        """On resistance of pnand, defined by stacked NMOS"""
+        is_nchannel = True
+        stack = 4
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)    

compiler/pgates/ptx.py

@@ -552,3 +552,10 @@ class ptx(design.design):
         """Return input to output polarity for module"""
         
         return True
+
+    def get_on_resistance(self):
+        """On resistance of pinv, defined by single nmos"""
+        is_nchannel = True
+        stack = 1
+        is_cell = False
+        return self.tr_r_on(self.nmos_width, is_nchannel, stack, is_cell)