Added special RC delay functions for the bitline and sense amp to match CACTI. Contains temporary parameters which need to be defined.

compiler/base/hierarchy_spice.py

@@ -430,7 +430,7 @@ class spice():
         r_wire = self.module_wire_r()
 
         tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2)
-        this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True)
+        this_delay = self.cacti_rc_delay(inrisetime, tf, 0.5, 0.5, True)
         inrisetime = this_delay / (1.0 - 0.5)
         return delay_data(this_delay, inrisetime)
 
@@ -518,6 +518,17 @@ class spice():
                               self.cell_name))
         return 0
 
+    def cacti_rc_delay(self, 
+                 inputramptime, # input rise time
+                 tf,            # time constant of gate
+                 vs1,           # threshold voltage
+                 vs2,           # threshold voltage
+                 rise):         # whether input rises or fall
+)       """By default, CACTI delay uses horowitz for gate delay.
+           Can be overriden in cases like bitline if equation is different.
+        """
+        return self.horowitz(inputramptime, tf, vs1, vs2, rise)
+        
     def horowitz(self, 
                  inputramptime, # input rise time
                  tf,            # time constant of gate

compiler/bitcells/bitcell_base.py

@@ -241,6 +241,7 @@ class bitcell_base(design.design):
         # graph implementation so array dims are all re-calculated here. May
         # be incorrect if dim calculations change 
         cells_in_col = OPTS.num_words/OPTS.words_per_row
+        debug.info(0,"l={}".format(cells_in_col*self.height))
         return cells_in_col*self.height*spice["wire_c_per_um"]
 
     def module_wire_r(self):
@@ -250,4 +251,14 @@ class bitcell_base(design.design):
         # be incorrect if dim calculations change 
         cells_in_col = OPTS.num_words/OPTS.words_per_row
         return cells_in_col*self.height*spice["wire_r_per_um"]   
-        
+        
+    def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise): 
+)       """ Special RC delay function used by CACTI for bitline delay
+        """
+        import math
+        vdd = 5 # temp value
+        if tf > 0.5*(vdd-spice["nom_threshold"])/rise:
+            delay = tf + (vdd-spice["nom_threshold"])/(2*rise)
+        else:
+            delay = math.sqrt(2*tf*(vdd-spice["nom_threshold"])/rise)
+        return delay  

compiler/custom/sense_amp.py

@@ -108,3 +108,16 @@ class sense_amp(design.design):
                                       stack,
                                       mult)                               
         return nmos_drain_c + pmos_drain_c + bl_pmos_drain_c
+
+    def cacti_rc_delay(self, inputramptime, tf, vs1, vs2, rise): 
+)       """ Special RC delay function used by CACTI for sense amp delay
+        """
+        import math
+        
+        # FIXME: temp values
+        c_senseamp = 0
+        g_m = 1
+        tau = c_senseamp/g_m
+        vdd = 5
+        v_sense = 1
+        return tau*math.log(vdd/v_sense)