 SWalker
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3271c5e73c
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fixing drc on rom bank, mostly spacing tweaks
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2023-10-31 23:24:21 -07:00 |
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SWalker
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75f7a5847f
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fixing contact placement for gf180 in rom
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2023-10-31 23:24:21 -07:00 |
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 Sage Walker
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b279791762
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added control buf test
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2023-10-31 23:24:21 -07:00 |
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SWalker
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a544abebf7
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fixed contact area issue
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2023-10-31 23:24:21 -07:00 |
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Sage Walker
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cb8567c66f
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spacing tweaks for gf180 address control gate
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2023-10-31 23:24:21 -07:00 |
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Sage Walker
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d6cb15c82d
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Switched to GF180D for extra metal layers, Fixed drc parameters so contacts are valid. ptx.py modified to achieve proper layer placement with gf180. ROM array and precharge DRC clean.
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2023-10-31 23:24:21 -07:00 |
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Sage Walker
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0040efb86f
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workaround for magic drc in gf180
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2023-10-31 23:24:21 -07:00 |
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Sage Walker
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b0a0226e87
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rom array compatability changes
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2023-10-31 23:24:21 -07:00 |
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 Hadir Khan
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7ce11eba52
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added pwell as a non-routing layer
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2023-10-31 23:24:21 -07:00 |
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Hadir Khan
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81b62ab13b
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added gf180mcu as the test tech target
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2023-10-31 23:24:21 -07:00 |
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 Jesse Cirimelli-Low
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d7c3bbea3e
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crba passing again norbl/leftrbl
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2023-10-28 18:05:07 -07:00 |
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 Eren Dogan
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fe379297be
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Add timestamps to the log file
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2023-10-05 14:55:05 -07:00 |
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 Sam Crow
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a5412902c6
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all control logic tests pass now
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2023-09-27 16:38:57 -07:00 |
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Sam Crow
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bf49ea744e
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force multi-delay chain pinouts to be user configurable
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2023-09-27 13:15:45 -07:00 |
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Sam Crow
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5b282df667
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Revert "add drc style drc(full) to run_drc.sh on Tim Edwards recommondation"
This reverts commit c4a14b9354.
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2023-09-26 11:37:04 -07:00 |
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Sam Crow
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c4a14b9354
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add drc style drc(full) to run_drc.sh on Tim Edwards recommondation
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2023-09-25 14:14:27 -07:00 |
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Jesse Cirimelli-Low
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2faa067ea6
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add support for col offset to rbc; fix rba mirroring
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2023-09-12 12:12:21 -07:00 |
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Jesse Cirimelli-Low
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0034798787
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both rbl replica array working
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2023-09-11 11:23:39 -07:00 |
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Eren Dogan
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b3e1a163d0
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Fix derouting wires in the gridless router
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2023-09-09 13:32:16 -07:00 |
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Jesse Cirimelli-Low
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e553f3db41
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fix sram.sp spare_wen
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2023-09-07 12:24:39 -07:00 |
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Eren Dogan
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995cc4f60f
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Fix typo
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2023-09-06 21:38:19 -07:00 |
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Eren Dogan
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3f2d61a0fa
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Prevent same file error when copying the config file (VLSIDA/PrivateRAM#108)
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2023-09-03 18:21:31 -07:00 |
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Jesse Cirimelli-Low
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eb82053ab8
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copy router from dev
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2023-09-03 13:16:18 -07:00 |
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Jesse Cirimelli-Low
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5605154cc2
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merge dev
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2023-09-02 12:27:38 -07:00 |
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Eren Dogan
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abb12bd785
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Increase non-preferred direction cost in router
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2023-09-02 08:00:58 -07:00 |
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Eren Dogan
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775922774a
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Use bbox trees to iterate over shapes in routing region efficiently
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2023-09-01 20:37:07 -07:00 |
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Jesse Cirimelli-Low
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066d00f44b
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increase power ring crba width for drc
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2023-09-01 02:02:41 -07:00 |
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Eren Dogan
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d9004f6de6
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Print more info for the routing processes
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2023-08-31 19:03:31 -07:00 |
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Eren Dogan
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8a60684e51
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Increase the routing region inflation to be safer
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2023-08-31 18:26:45 -07:00 |
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Eren Dogan
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a9e63efad7
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Increase via cost in router
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2023-08-31 18:26:04 -07:00 |
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Jesse Cirimelli-Low
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c9a848550c
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Revert "merge dev"
This reverts commit daec840888, reversing
changes made to 29e80e8f25.
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2023-08-30 22:40:35 -07:00 |
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Jesse Cirimelli-Low
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daec840888
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merge dev
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2023-08-30 22:04:42 -07:00 |
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Jesse Cirimelli-Low
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0cba6a6050
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single port sky130 crba passing lvs
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2023-08-30 20:59:02 -07:00 |
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Eren Dogan
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56bee27ee3
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Don't write/read gds files unnecessarily for router
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2023-08-29 21:45:52 -07:00 |
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Jesse Cirimelli-Low
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8f2e4c6914
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power ring working
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2023-08-28 22:15:05 -07:00 |
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Jesse Cirimelli-Low
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8794070ebc
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various refactor changes
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2023-08-28 12:31:55 -07:00 |
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Eren Dogan
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e12ab68362
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Simplify closest edge calculation in signal escape router
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2023-08-28 10:38:53 -07:00 |
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Eren Dogan
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fa5de05be3
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Merge branch 'dev' into gridless_router
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2023-08-27 21:17:58 -07:00 |
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Eren Dogan
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53cc99f5c1
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Perform signal escape routing in smaller regions
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2023-08-27 21:16:34 -07:00 |
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Eren Dogan
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9df3c2ac59
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Return the path in source-to-target order
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2023-08-27 21:15:25 -07:00 |
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Eren Dogan
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141a4e3380
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Don't scale the routing region if no path is found
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2023-08-27 15:42:09 -07:00 |
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Jesse Cirimelli-Low
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ba51149dce
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placement working for sp capped rba, need fix rowcap patterns
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2023-08-26 18:54:07 -07:00 |
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Jesse Cirimelli-Low
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036cc54b99
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rba done w/o wordline
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2023-08-24 02:55:45 -07:00 |
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Jesse Cirimelli-Low
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450f8ab0c3
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replica col generating, funny dummy cell placement
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2023-08-22 00:45:57 -07:00 |
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Jesse Cirimelli-Low
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f890160601
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add nwell routing in bca
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2023-08-21 20:12:36 -07:00 |
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Jesse Cirimelli-Low
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5a6c78865d
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singleport bitcell array laying out
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2023-08-21 19:24:06 -07:00 |
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Jesse Cirimelli-Low
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9ac894e2ef
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update bitcell array trimming
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2023-08-15 11:30:16 -07:00 |
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Sam Crow
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bb47452baf
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reapply commit c8a06a1 patch that was incorrectly reverted
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2023-08-15 11:07:04 -07:00 |
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Jesse Cirimelli-Low
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e4c15d33c4
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Merge branch 'singleport_refactor' of github.com:VLSIDA/PrivateRAM into singleport_refactor
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2023-08-14 18:53:22 -07:00 |
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Sam Crow
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cd1b0f973d
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Revert pin/net spice object work
This reverts commits 01116 6e3e9 2ced8 c67fd 2b9e7 bfabe 09aa3 5907c aa717 478c7 45b88 d0339 e15fe 7581d c8c43 146ef
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2023-08-14 18:44:51 -07:00 |
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