mirror of https://github.com/VLSIDA/OpenRAM.git
add support for col offset to rbc; fix rba mirroring
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0034798787
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@ -87,7 +87,7 @@ class replica_bitcell_array(bitcell_base_array):
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if port in self.left_rbl:
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# These go top down starting from the bottom of the bitcell array.
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replica_bit = self.rbl[0] - port - 1
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column_offset = len(self.left_rbl)
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column_offset = 0
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elif port in self.right_rbl:
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# These go bottom up starting from the top of the bitcell array.
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replica_bit = self.rbl[0] + self.row_size + port - 1
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@ -104,7 +104,16 @@ class replica_column(bitcell_base_array):
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True)
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else:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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current_row += 1
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if self.cell.mirror.y:
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print(self.column_offset)
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for row in range(self.total_size):
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if self.column_offset % 2 == 0:
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if core_block[row][0].mirror=='MX':
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core_block[row][0].mirror='XY'
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else:
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core_block[row][0].mirror='MY'
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self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.total_size, num_cols=self.column_size, name_template="rbc_r{0}_c{1}")
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self.pattern.connect_array()
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