mirror of https://github.com/VLSIDA/OpenRAM.git
remove print statements
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6f9618f28a
commit
c1acdadd81
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@ -49,10 +49,8 @@ class pattern():
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self.num_cores_y = num_cores_y
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if num_cores_x == 0:
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self.num_cores_x = ceil(num_cols/len(core_block[0]))
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print('num_cores_x:', self.num_cores_x)
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if num_cores_y == 0:
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self.num_cores_y = ceil(num_rows/len(core_block))
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print('num_cores_y:', self.num_cores_y)
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self.cores_per_x_block = cores_per_x_block
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self.cores_per_y_block = cores_per_y_block
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@ -63,7 +61,6 @@ class pattern():
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self.initial_y_block = initial_y_block
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self.final_x_block = final_x_block
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self.final_y_block = final_y_block
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print(self.num_cols)
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if not OPTS.netlist_only:
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self.verify_interblock_dimensions()
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@ -116,16 +113,11 @@ class pattern():
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self.bit_rows.append(0)
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if(len(self.bit_cols) <= row + dr):
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self.bit_cols.append(0)
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# print(self.bit_rows[col+dc], self.num_rows, self.bit_cols[row+dr], self.num_cols)
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if(self.bit_rows[col+dc] < self.num_rows and self.bit_cols[row+dr] < self.num_cols):
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if(inst.is_bitcell):
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self.bit_rows[col+dc] += 1
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self.bit_cols[row+dr] += 1
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print(self.bit_rows)
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print(self.bit_cols)
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print('-----------------------------------')
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self.parent_design.cell_inst[row + dr, col + dc] = self.parent_design.add_existing_inst(inst,"bit_r{}_c{}".format(row +dr, col+dc))
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print('inst:', row+dr, col+dc)
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self.parent_design.connect_inst(self.parent_design.get_bitcell_pins(row+dr, col+dc))
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def connect_array(self) -> None:
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@ -135,14 +127,10 @@ class pattern():
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col = 0
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for i in range(self.num_cores_y):
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for j in range (self.num_cores_x):
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print("connecting {} {}".format(row,col))
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self.connect_block(self.core_block, col, row)
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col += len(self.core_block[0])
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col = 0
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row += len(self.core_block)
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# print(self.bit_rows)
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# print(self.bit_cols)
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print(self.parent_design.cell_inst)
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def place_inst(self, inst, offset) -> None:
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x = offset[0]
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@ -188,13 +176,10 @@ class pattern():
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col = 0
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place_x = 0
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for j in range (self.num_cores_x):
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print("placing {} {}".format(row,col))
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self.place_block(self.core_block, row, col, place_x, place_y)
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place_x += self.core_block_width
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col += len(self.core_block[0])
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if(self.bit_rows.count(self.num_rows) == self.num_cols and self.bit_cols.count(self.bit_cols) == self.num_rows):
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print(self.bit_rows)
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print(self.bit_cols)
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return
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row += len(self.core_block)
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