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OpenRAM
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working on updated placemet code

This commit is contained in:
Jesse Cirimelli-Low 2023-07-30 20:06:40 -07:00
parent 4d6e836b20
commit 811eb43459
3 changed files with 34 additions and 17 deletions
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7
compiler/modules/bitcell_array.py
View File

@ -61,10 +61,11 @@ class bitcell_array(bitcell_base_array):
def create_instances(self):
self.cell_inst={}
core_block = [[0 for x in range(2)] for y in range(2)]
# block[col][row
core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True)
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True)
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True)
core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True, mirror='MX')
core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True, mirror='MY')
core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True, mirror='XY')
self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
self.pattern.connect_array()

28
compiler/modules/dummy_array.py
View File

@ -6,7 +6,8 @@
from openram.sram_factory import factory
from openram import OPTS
from .bitcell_base_array import bitcell_base_array
from openram.base import geometry
from .pattern import pattern
class dummy_array(bitcell_base_array):
"""
@ -32,7 +33,7 @@ class dummy_array(bitcell_base_array):
def create_layout(self):
self.place_array("dummy_r{0}_c{1}", self.mirror)
self.place_array()
self.add_layout_pins()
@ -50,13 +51,22 @@ class dummy_array(bitcell_base_array):
def create_instances(self):
""" Create the module instances used in this design """
self.cell_inst = {}
for col in range(self.column_size):
for row in range(self.row_size):
name = "bit_r{0}_c{1}".format(row, col)
self.cell_inst[row, col]=self.add_inst(name=name,
mod=self.dummy_cell)
self.connect_inst(self.get_bitcell_pins(row, col))
self.cell_inst={}
core_block = [[0 for x in range(2)] for y in range(2)]
if not self.mirror:
core_block[0][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
core_block[0][1] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
core_block[1][0] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
core_block[1][1] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
else:
core_block[0][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
core_block[0][1] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
core_block[1][0] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True)
core_block[1][1] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
self.pattern.connect_array()
def add_pins(self):
# bitline pins are not added because they are floating

16
compiler/modules/pattern.py
View File

@ -177,13 +177,19 @@ class pattern():
place_x = 0
for j in range (self.num_cores_x):
self.place_block(self.core_block, row, col, place_x, place_y)
place_x += self.core_block_width
col += len(self.core_block[0])
if(self.bit_rows.count(self.num_rows) == self.num_cols and self.bit_cols.count(self.bit_cols) == self.num_rows):
self.parent_design.width = place_x
self.parent_design.height= place_y
print("early")
return
self.parent_design.width = place_x
place_x += self.core_block_width
col += len(self.core_block[0])
row += len(self.core_block)
self.parent_design.height = place_y
place_y += self.core_block_height
self.parent_design.width = place_x
self.parent_design.height = place_y
print(self.parent_design.width, self.parent_design.height)
print("late")