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fix sram.sp spare_wen

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Jesse Cirimelli-Low
2023-09-07 12:24:39 -07:00
parent eb82053ab8
commit e553f3db41
1 changed files with 4 additions and 1 deletions
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compiler/modules/sram_1bank.py
+4 -1
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@@ -662,7 +662,10 @@ class sram_1bank(design, verilog, lef):
inputs = []
outputs = []
for bit in range(self.num_spare_cols):
inputs.append("spare_wen{}[{}]".format(port, bit))
if self.num_spare_cols == 1:
inputs.append("spare_wen{}".format(port))
else:
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}_{}".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)