mirror of https://github.com/VLSIDA/OpenRAM.git
Don't write/read gds files unnecessarily for router
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b525ba60a0
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@ -59,6 +59,8 @@ class router(router_tech):
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def prepare_gds_reader(self):
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""" Write the current layout to a temporary file to read the layout. """
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# NOTE: Avoid using this function if possible since it is too slow to
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# write/read these files
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self.design.gds_write(self.gds_filename)
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self.layout = gdsMill.VlsiLayout(units=GDS["unit"])
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self.reader = gdsMill.Gds2reader(self.layout)
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@ -109,16 +111,26 @@ class router(router_tech):
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self.all_pins.update(pin_set)
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def find_blockages(self, name="blockage"):
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def find_blockages(self, name="blockage", shape_list=None):
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""" Find all blockages in the routing layers. """
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debug.info(2, "Finding blockages...")
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for lpp in [self.vert_lpp, self.horiz_lpp]:
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shapes = self.layout.getAllShapes(lpp)
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# If the list of shapes is given, don't get them from gdsMill
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if shape_list is None:
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shapes = self.layout.getAllShapes(lpp)
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else:
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shapes = shape_list
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for boundary in shapes:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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if shape_list is not None:
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if boundary.lpp != lpp:
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continue
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ll = boundary.ll()
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ur = boundary.ur()
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else:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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rect = [ll, ur]
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new_shape = graph_shape(name, rect, lpp)
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new_shape = self.inflate_shape(new_shape)
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@ -132,20 +144,28 @@ class router(router_tech):
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self.blockages.append(new_shape)
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def find_vias(self):
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def find_vias(self, shape_list=None):
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""" Find all vias in the routing layers. """
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debug.info(2, "Finding vias...")
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# Prepare lpp values here
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from openram.tech import layer
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via_lpp = layer[self.via_layer_name]
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valid_lpp = self.horiz_lpp
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valid_lpp = self.horiz_lpp # Just a temporary lpp to prevent errors
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shapes = self.layout.getAllShapes(via_lpp)
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# If the list of shapes is given, don't get them from gdsMill
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if shape_list is None:
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shapes = self.layout.getAllShapes(via_lpp)
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else:
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shapes = shape_list
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for boundary in shapes:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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if shape_list is not None:
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ll = boundary.ll()
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ur = boundary.ur()
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else:
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# gdsMill boundaries are in (left, bottom, right, top) order
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ll = vector(boundary[0], boundary[1])
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ur = vector(boundary[2], boundary[3])
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rect = [ll, ur]
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new_shape = graph_shape("via", rect, valid_lpp)
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# Skip this via if it's contained by an existing via blockage
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@ -264,7 +284,8 @@ class router(router_tech):
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working for this router.
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"""
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new_shapes = []
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new_wires = []
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new_vias = []
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for i in range(0, len(nodes) - 1):
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start = nodes[i].center
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end = nodes[i + 1].center
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@ -275,15 +296,16 @@ class router(router_tech):
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offset.y - self.half_wire)
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if direction == (1, 1): # Via
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offset = vector(start.x, start.y)
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self.design.add_via_center(layers=self.layers,
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offset=offset)
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via = self.design.add_via_center(layers=self.layers,
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offset=offset)
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new_vias.append(via)
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else: # Wire
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shape = self.design.add_rect(layer=self.get_layer(start.z),
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offset=offset,
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width=abs(diff.x) + self.track_wire,
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height=abs(diff.y) + self.track_wire)
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new_shapes.append(shape)
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return new_shapes
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wire = self.design.add_rect(layer=self.get_layer(start.z),
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offset=offset,
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width=abs(diff.x) + self.track_wire,
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height=abs(diff.y) + self.track_wire)
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new_wires.append(wire)
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return new_wires, new_vias
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def write_debug_gds(self, gds_name, g=None, source=None, target=None):
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@ -67,12 +67,11 @@ class signal_escape_router(router):
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self.write_debug_gds(gds_name="{}error.gds".format(OPTS.openram_temp), g=g, source=source, target=target)
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debug.error("Couldn't route from {} to {}.".format(source, target), -1)
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# Create the path shapes on layout
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new_shapes = self.add_path(path)
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self.new_pins[source.name] = new_shapes[-1]
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new_wires, new_vias = self.add_path(path)
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self.new_pins[source.name] = new_wires[-1]
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# Find the recently added shapes
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self.prepare_gds_reader()
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self.find_blockages(name)
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self.find_vias()
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self.find_blockages(name, new_wires)
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self.find_vias(new_vias)
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self.replace_layout_pins()
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@ -73,7 +73,7 @@ class supply_router(router):
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for source, target in self.get_mst_pairs(list(pins)):
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# Create the graph
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g = graph(self)
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region = g.create_graph(source, target)
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g.create_graph(source, target)
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# Find the shortest path from source to target
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path = g.find_shortest_path()
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# If no path is found, throw an error
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@ -81,11 +81,10 @@ class supply_router(router):
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self.write_debug_gds(gds_name="{}error.gds".format(OPTS.openram_temp), g=g, source=source, target=target)
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debug.error("Couldn't route from {} to {}.".format(source, target), -1)
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# Create the path shapes on layout
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self.add_path(path)
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new_wires, new_vias = self.add_path(path)
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# Find the recently added shapes
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self.prepare_gds_reader()
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self.find_blockages(pin_name)
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self.find_vias()
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self.find_blockages(pin_name, new_wires)
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self.find_vias(new_vias)
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def add_side_pin(self, pin_name, side, num_vias=3, num_fake_pins=4):
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