mirror of https://github.com/VLSIDA/OpenRAM.git
remove whitespace
This commit is contained in:
Jesse Cirimelli-Low
parent
61cfa55d75
commit
5e01bad2ee
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@ -66,7 +66,7 @@ class bitcell_array(bitcell_base_array):
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self.pattern = pattern(self, "bitcell_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
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self.pattern.connect_array()
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for key in self.cell_inst.keys():
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if key != (0,0):
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self.trim_insts.add(self.cell_inst[key].name)
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@ -6,7 +6,7 @@
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from openram.sram_factory import factory
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from openram.base import geometry
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from openram.base import geometry
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from .pattern import pattern
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class dummy_array(bitcell_base_array):
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@ -53,8 +53,8 @@ class dummy_array(bitcell_base_array):
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""" Create the module instances used in this design """
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self.cell_inst={}
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core_block = [[0 for x in range(1)] for y in range(2)]
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core_block[(0+self.mirror) %2][0] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[(1+self.mirror) %2][0] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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core_block[0][(0+self.mirror) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[0][(1+self.mirror) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size)
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@ -1,3 +1,8 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram import debug
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from openram.base.geometry import instance,geometry
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from typing import List
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@ -7,7 +12,7 @@ from openram.globals import OPTS
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from math import ceil
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class pattern():
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"""
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This class is used to desribe the internals of a bitcell array. It describes
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This class is used to desribe the internals of a bitcell array. It describes
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instance modules, rotation, and ordering
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"""
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@ -22,18 +27,18 @@ class pattern():
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num_cores_y: Optional[int] = 0,
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cores_per_x_block: int = 1,
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cores_per_y_block: int = 1,
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x_block: Optional[block] = None,
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y_block: Optional[block] = None,
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x_block: Optional[block] = None,
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y_block: Optional[block] = None,
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xy_block: Optional[block] = None,
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initial_x_block:bool = False,
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initial_y_block:bool = False,
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final_x_block:bool = False,
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final_y_block:bool = False
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):
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):
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"""
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a "block" is a 2d list of instances
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core_block defines the main block that is tiled
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num_core defines the number of times the core block is to be tiled
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num_core defines the number of times the core block is to be tiled
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(i.e. bitcells in dimension / bitcells in core_block)
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x_block defines a block that is inserted to the right of the core_block
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y_block defines a block that is inserted below the core block
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@ -43,7 +48,7 @@ class pattern():
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self.parent_design = parent_design
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self.name = name
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self.core_block = core_block
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self.num_rows = num_rows
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self.num_rows = num_rows
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self.num_cols = num_cols
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self.num_cores_x = num_cores_x
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self.num_cores_y = num_cores_y
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@ -62,22 +67,22 @@ class pattern():
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self.final_x_block = final_x_block
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self.final_y_block = final_y_block
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if not OPTS.netlist_only:
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self.verify_interblock_dimensions()
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self.verify_interblock_dimensions()
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def compute_and_verify_intrablock_dimensions(self, block: block) -> List[int]:
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for row in block:
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row_height = row[0].height
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for inst in row:
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debug.check(row_height == inst.height, "intrablock instances within the same row are different heights")
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for y in range(len(block[0])):
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debug.check(all([row[y].width for row in block]), "intrablock instances within the same column are different widths")
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block_width = sum([instance.width for instance in block[0]])
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block_height = sum([row[0].height for row in block])
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block_height = sum([row[0].height for row in block])
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return [block_width, block_height]
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def verify_interblock_dimensions(self) -> None:
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"""
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Ensure the individual blocks are valid and interblock dimensions are valid
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@ -95,14 +100,14 @@ class pattern():
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(self.y_block_width, self.y_block_height) = self.compute_and_verify_intrablock_dimensions(self.y_block)
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if self.xy_block:
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(self.xy_block_width, self.xy_block_height) = self.compute_and_verify_intrablock_dimensions(self.xy_block)
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if(self.x_block):
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if(self.x_block):
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debug.check(self.core_block_width * self.cores_per_x_block == self.x_block_width, "core_block does not align with x_block")
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if(self.y_block):
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debug.check(self.core_block_height * self.cores_per_y_block == self.y_block_height, "core_block does not aligns with y_block")
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if(self.xy_block):
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debug.check(self.xy_block_height == self.x_block_height, "xy_block does not align with x_block")
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debug.check(self.xy_block_width == self.y_block_width, "xy_block does not align with y_block")
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def connect_block(self, block: block, col: int, row: int):
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for dr in range(len(block)):
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@ -141,7 +146,7 @@ class pattern():
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x += inst.width
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inst.place((x, y), inst.mirror, inst.rotate)
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def place_block(self, block: block, row: int, col: int, place_x: float, place_y: float, bx, by):
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x_offset = 0
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@ -87,7 +87,7 @@ class replica_column(bitcell_base_array):
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def create_instances(self):
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self.cell_inst = {}
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core_block = [[0 for x in range(1)] for y in range(self.total_size)]
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core_block = [[0 for x in range(1)] for y in range(self.total_size)]
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current_row = self.row_start
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for row in range(self.total_size):
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@ -99,7 +99,7 @@ class replica_column(bitcell_base_array):
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True, mirror='MX')
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else:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.replica_cell, is_bitcell=True)
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else:
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else:
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if current_row %2:
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core_block[row][0] = geometry.instance("rbc_{}".format(row), mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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else:
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