mirror of https://github.com/VLSIDA/OpenRAM.git
Use the same inflating rules for all shapes in router
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@ -145,7 +145,7 @@ class router(router_tech):
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# Skip this via if it's contained by an existing via blockage
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if new_shape.contained_by_any(self.vias):
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continue
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self.vias.append(self.inflate_shape(new_shape, is_via=True))
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self.vias.append(self.inflate_shape(new_shape))
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def convert_vias(self):
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@ -188,32 +188,31 @@ class router(router_tech):
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break
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def inflate_shape(self, shape, is_pin=False, is_via=False):
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def inflate_shape(self, shape):
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""" Inflate a given shape with spacing rules. """
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# Pins must keep their center lines away from any blockage to prevent
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# the nodes from being unconnected
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if is_pin:
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xdiff = self.layer_widths[0] - shape.width()
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ydiff = self.layer_widths[0] - shape.height()
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diff = max(xdiff, ydiff) / 2
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spacing = self.track_space + drc["grid"]
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if diff > 0:
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spacing += diff
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# Vias are inflated by the maximum spacing rule
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elif is_via:
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spacing = self.track_space
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# Blockages are inflated by their layer's corresponding spacing rule
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# Get the layer-specific spacing rule
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if self.get_zindex(shape.lpp) == 1:
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spacing = self.vert_layer_spacing
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else:
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if self.get_zindex(shape.lpp) == 1:
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spacing = self.vert_layer_spacing
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else:
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spacing = self.horiz_layer_spacing
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spacing = self.horiz_layer_spacing
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# If the shape is wider than the supply wire width, its spacing can be
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# different
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wide = min(shape.width(), shape.height())
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if wide > self.layer_widths[0]:
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spacing = self.get_layer_space(self.get_zindex(shape.lpp), wide)
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# Shapes must keep their center lines away from any blockage to prevent
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# the nodes from being unconnected
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xdiff = self.track_wire - shape.width()
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ydiff = self.track_wire - shape.height()
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diff = snap(max(xdiff, ydiff) / 2)
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if diff > 0:
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spacing += diff
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# Add minimum unit to the spacing to keep nodes out of inflated regions
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spacing += drc["grid"]
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return shape.inflated_pin(spacing=spacing,
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extra_spacing=self.half_wire)
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@ -50,9 +50,10 @@ class signal_escape_router(router):
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# Add vdd and gnd pins as blockages as well
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# NOTE: This is done to make vdd and gnd pins DRC-safe
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for pin in self.all_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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self.blockages.append(self.inflate_shape(pin))
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# Route vdd and gnd
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i = 0
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for source, target, _ in self.get_route_pairs(pin_names):
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# Change fake pin's name so the graph will treat it as routable
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target.name = source.name
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@ -65,7 +65,7 @@ class supply_router(router):
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# Add vdd and gnd pins as blockages as well
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# NOTE: This is done to make vdd and gnd pins DRC-safe
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for pin in self.all_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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self.blockages.append(self.inflate_shape(pin))
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# Route vdd and gnd
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for pin_name in [vdd_name, gnd_name]:
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@ -239,7 +239,7 @@ class supply_router(router):
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# Save side pins for routing
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self.new_pins[pin_name] = new_pins
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for pin in new_pins:
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self.blockages.append(self.inflate_shape(pin, is_pin=True))
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self.blockages.append(self.inflate_shape(pin))
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def get_mst_pairs(self, pins):
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